luke
/
abc
mirror of https://github.com/YosysHQ/abc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,977 Commits 27 Branches 57 Tags 58 MiB
Commit Graph

2758 Commits

Author SHA1 Message Date
Tobias Wiersema ca710b3dda Add inv_get -f to read flop names from GIA 2021-08-19 17:57:19 +02:00
Alan Mishchenko 4da6cc8904 Improving AIG to Verilog converter. 2021-08-17 16:52:29 -07:00
Alan Mishchenko e9b487666d Suggested changes to collect and pass timing information (unused variable). 2021-08-12 18:27:40 -07:00
Alan Mishchenko 0deb8bf632 Suggested changes to collect and pass timing information (compiler issues). 2021-08-12 18:26:37 -07:00
Alan Mishchenko e8ac47641f Suggested changes to collect and pass timing information. 2021-08-12 18:25:00 -07:00
Alan Mishchenko 99ab99bfa6 Making &cec support the miter circuit. 2021-08-05 15:05:59 -07:00
Alan Mishchenko ddc574a954 Supporting simple operators in NDR. 2021-08-05 14:01:55 -07:00
Alan Mishchenko ab29dad7f4 Adding node ordering options to command &dfs. 2021-08-05 11:07:16 -07:00
Alan Mishchenko 5f8d4e72d1 Experiments with LUT mapping for small functions. 2021-08-02 16:46:56 -07:00
Alan Mishchenko 4cf906d2fc Experiments with LUT mapping for small functions. 2021-08-01 12:13:27 -07:00
Alan Mishchenko e162a26197 Allow retiming to skip some logic. 2021-07-31 22:46:47 -07:00
Alan Mishchenko 692dd76319 Upgrading choice computation. 2021-07-31 15:34:46 -07:00
Alan Mishchenko d925e4802c Experiments with cofactoring. 2021-07-31 11:30:19 -07:00
Alan Mishchenko a162b1f47a Experimental simulation commands. 2021-07-25 14:11:34 -07:00
Alan Mishchenko 62180f3576 Command to move CI/CO names. 2021-07-16 13:46:41 -07:00
Alan Mishchenko 6e5a797a6d Command to move CI/CO names. 2021-07-16 13:44:38 -07:00
Alan Mishchenko d9aeaade3b Several unrelated changes. 2021-07-15 18:23:04 -07:00
Alan Mishchenko 3e67d167f5 Experiments with LUT mapping for small functions. 2021-07-13 19:05:02 -07:00
Alan Mishchenko 9fac6c7a8b Experiments with CEC. 2021-07-10 10:50:33 -07:00
Alan Mishchenko 5a135c8799 Experiments with MUX decomposition. 2021-07-08 21:42:15 -07:00
Alan Mishchenko 28ba2c5213 Adding place holder file for resub experiments. 2021-06-24 19:18:28 -07:00
Alan Mishchenko b4f099c511 Experiments with LUT mapping for small functions. 2021-06-19 19:26:41 -07:00
Alan Mishchenko 7d18d6b7aa Experiments with cut computation. 2021-06-05 17:48:12 -07:00
Alan Mishchenko 84ec53fbf9 Disabled special handling of 2-input LUTs. 2021-06-03 08:39:30 -07:00
Alan Mishchenko 49078ffebf Updating LUT synthesis code. 2021-05-25 23:12:30 -07:00
Alan Mishchenko d35b05859c Adding command &extract. 2021-05-18 16:42:16 -07:00
Alan Mishchenko 0ce11851bc Updating LUT synthesis code. 2021-05-16 20:33:53 -07:00
Alan Mishchenko 610a3d3fc2 Adding switch muxes -a to create networks of ADDs. 2021-05-15 13:28:06 -07:00
Alan Mishchenko ed13c6d4d2 Updating LUT synthesis code. 2021-05-11 17:45:20 -07:00
Alan Mishchenko e6a47c3e41 Disable cube-sort when deriving SOPs. 2021-05-11 15:54:43 -07:00
Alan Mishchenko aa9fe1f240 Updating LUT synthesis code. 2021-05-11 15:04:15 -07:00
Alan Mishchenko 76bed2055c Updating LUT synthesis code. 2021-05-08 20:10:44 -07:00
Alan Mishchenko 17476146ca Fixing mismatch in &cec -x which should return undecided rather than non-equivalent when the miter cannot be reduced to constant 0. 2021-05-08 19:07:10 -07:00
Alan Mishchenko 7d90895dcf Experiments with LUT mapping for small functions. 2021-05-01 22:44:29 -07:00
Alan Mishchenko 645752f7d6 Making sure read_bench can read nodes up to 15 inputs. 2021-04-30 16:12:15 -07:00
Alan Mishchenko 9b75906740 Several changes for standard mapping. 2021-04-28 00:11:02 -07:00
Alan Mishchenko de71e5f610 Passing node labels. 2021-04-26 18:52:44 -07:00
Alan Mishchenko 75981f7fee Computing sum of PO support sizes. 2021-04-09 13:46:52 -07:00
Alan Mishchenko 9145a5c20d An option to extend the number of primary inputs. 2021-03-28 15:40:27 -10:00
Alan Mishchenko 18088bd7dc Compiler warnings. 2021-03-28 14:54:07 -10:00
Alan Mishchenko 6a03ece98d Command &iwls21test for evaluating the results of 2021 IWLS Contest. 2021-03-28 14:49:27 -10:00
Alan Mishchenko 66098723eb Adding a random seed to control randomness in 'permute' (correction). 2021-03-11 17:50:56 -10:00
Alan Mishchenko b2ca837521 Adding a random seed to control randomness in 'permute'. 2021-03-11 17:45:01 -10:00
Alan Mishchenko cd8843c06c Preventing command history from being overwritten by internal scripts. 2021-01-09 13:06:45 -08:00
Alan Mishchenko f06217e25a Compiler warnings. 2020-12-21 12:45:50 -08:00
Alan Mishchenko 73dcdab6d8 Adding solver type in &sat. 2020-12-16 22:04:06 -08:00
Alan Mishchenko 8066fdbcb5 Adding generation of combinational speculative miters. 2020-12-16 10:31:25 -08:00
Alan Mishchenko 06094ade87 Adding switch to replace proved outputs by const0. 2020-12-16 00:06:31 -08:00
Alan Mishchenko 901560bb23 Deriving equivalent nets from proved equivalences. 2020-12-09 21:59:49 -10:00
Alan Mishchenko 5b8e56b2e5 Adding timeout to several commands. 2020-12-07 17:15:31 -10:00
Alan Mishchenko 6eee09c51c Added switch -y to control blasting divide-by-zero condition. 2020-11-29 13:46:21 -10:00
Alan Mishchenko d4fb192575 Renaming one command. 2020-11-23 07:31:54 -10:00
Alan Mishchenko 22f36299aa Added an option to keep PI/PO names unchanged in 'short_names'. 2020-11-22 23:02:35 -10:00
Alan Mishchenko 2e92256fb7 Passing conflict limit to &cec. 2020-11-22 21:34:33 -10:00
Alan Mishchenko 48f71adacd Integration with several commands. 2020-11-19 19:22:27 -08:00
Alan Mishchenko dd07ec57be Extending sweeper to handle XORs. 2020-11-15 19:02:41 -08:00
Alan Mishchenko bab4c1ddfc Upgrading the SAT solvers. 2020-11-14 14:23:49 -08:00
Alan Mishchenko cc840d8bd8 Improvements to the SAT sweeper. 2020-11-13 19:12:34 -08:00
Alan Mishchenko 22388f901a Adding and integrating new SAT solver APIs. 2020-11-13 10:29:31 -08:00
Alan Mishchenko b3d3f7dd3a Duplicating Glucose package. 2020-11-12 23:57:46 -08:00
Alan Mishchenko c0bb4bb047 Experiments with SAT sweeping. 2020-11-10 23:15:42 -08:00
Alan Mishchenko 3da87edbb4 Setting default conflict limit in &fraig to be high. 2020-11-09 15:25:32 -08:00
Alan Mishchenko 40bfe2fb88 Experiments with SAT sweeping. 2020-11-09 13:24:07 -08:00
Alan Mishchenko ce95366e51 Trying to explicitly compute don't-cares during optimization. 2020-11-01 14:23:17 -08:00
Alan Mishchenko 3a7b3d27f1 Experimental cost function in technology mapping. 2020-11-01 09:56:01 -08:00
Alan Mishchenko 2325cd77e3 Adding an option to write Verilog with LUT instances (compiler warnings). 2020-10-31 16:14:52 -07:00
Alan Mishchenko f9af41ba1b Adding an option to write Verilog with LUT instances. 2020-10-31 15:08:40 -07:00
Alan Mishchenko b2aa245eaa Fixing a clang error related to 'unlink'. 2020-10-09 23:28:23 -07:00
Alan Mishchenko ada073110e New command 'read_sf'. 2020-10-01 21:24:32 -07:00
Alan Mishchenko f21bafeb23 Changing SAT sweepers (ifraig and &fraig) to be stronger by default. 2020-09-24 23:49:01 -07:00
Alan Mishchenko 083c1218e5 Improving MFFC computation code. 2020-09-17 13:04:09 -07:00
Alan Mishchenko bab462d5cd Compiler warnings. 2020-09-13 20:33:59 -07:00
Alan Mishchenko 07bf95f480 Experiments with iterative synthesis. 2020-09-13 19:17:16 -07:00
Alan Mishchenko d556ad65ff Adding switch &cec -w to print SAT solver stats. 2020-09-06 23:15:21 -07:00
Alan Mishchenko fe968e9d79 Fixing a typo in setting the miter type. 2020-09-06 22:53:24 -07:00
Alan Mishchenko 8ef4404542 Verifying new resub code. 2020-09-06 22:34:45 -07:00
Alan Mishchenko 4b4646283f Experiments with ICCAD CAD benchmarks (Problem A). 2020-09-03 16:43:53 -07:00
Alan Mishchenko 26e03ef6a0 Experiments with window computation. 2020-08-15 17:12:41 -07:00
Alan Mishchenko 850d39fec3 Making &cec use precomputed simulation info. 2020-08-12 19:32:42 -07:00
Alan Mishchenko aaeadb1438 New ways of reading MiniAIG. 2020-07-29 19:48:36 -07:00
Alan Mishchenko 22d9b1d38b Experiment with structural similarity. 2020-07-16 20:33:03 -07:00
Alan Mishchenko 2ba092e4cc Fixing commands 'putontop' and 'topmost'; adding command 'bottommost'. 2020-07-11 10:14:43 -07:00
Alan Mishchenko 83f54185ef Bug fix in &cec (properly updating the status after the corner case bug fix\). 2020-06-24 10:57:47 -07:00
Alan Mishchenko 322cea8234 Bug fix in &cec (handling the case when the miter is disproved by the all-0 pattern). 2020-06-24 10:20:28 -07:00
Alan Mishchenko 58e3a5caff Compiler error. 2020-06-04 16:48:06 -07:00
Alan Mishchenko a3c6f33a87 Experimental simulation. 2020-06-04 16:24:43 -07:00
Alan Mishchenko 491e4ebfd1 Experimental simulation. 2020-06-03 14:52:42 -07:00
Alan Mishchenko 97c826a6e6 Dumping BDD variable order after 'clp'. 2020-05-18 16:02:57 -07:00
Alan Mishchenko 0ae0744e73 Experimental resubstitution. 2020-05-15 22:11:10 -07:00
Alan Mishchenko 1c0ea1022f Adding new utility procedures. 2020-05-11 17:08:00 -07:00
Alan Mishchenko a3ada00d86 Adding new utility procedures. 2020-05-10 19:44:59 -07:00
Alan Mishchenko f8b6d615bf Fixing the accidentally broken build. 2020-05-06 12:48:11 -07:00
Alan Mishchenko f543d39ec8 Experiment with permutations. 2020-05-03 21:09:02 -07:00
Alan Mishchenko f026e65339 Compiler warnings and errors. 2020-05-03 19:09:02 -07:00
Alan Mishchenko d51f798956 Experimental resubstitution. 2020-05-03 10:32:30 -07:00
alanminko 8de27b691b
Merge pull request #57 from whitequark/patch-1 
Make use of setrlimit conditional on ABC_NO_RLIMIT
 2020-04-30 14:03:26 -07:00
whitequark 8afd927d60 Make use of setrlimit conditional on ABC_NO_RLIMIT. 
This is useful for POSIX-like platforms that do not have rlimit,
such as WASI.
 2020-04-30 02:17:03 +00:00
Alan Mishchenko cf1fdc82e4 Bug fix in 'resub' to enable additional divisors, by Siang-Yun Lee. 2020-04-27 18:52:19 -07:00
Alan Mishchenko ea1fbfc971 New AIG restructuring feature. 2020-04-23 15:33:49 -07:00
Alan Mishchenko 978b5db039 Fix a bug in comb loop detection. 2020-04-22 16:49:21 -07:00