mirror of https://github.com/YosysHQ/abc.git
Bug fix in &cec (handling the case when the miter is disproved by the all-0 pattern).
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@ -36950,13 +36950,31 @@ int Abc_CommandAbc9Cec( Abc_Frame_t * pAbc, int argc, char ** argv )
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}
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else
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{
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Gia_Man_t * pTemp;
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abctime clk = Abc_Clock();
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Gia_Obj_t * pObj; int i;
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if ( !pPars->fSilent )
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Abc_Print( 1, "Assuming the current network is a single-output miter.\n" );
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pTemp = Gia_ManDemiterToDual( pAbc->pGia );
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pAbc->Status = Cec_ManVerify( pTemp, pPars );
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ABC_SWAP( Abc_Cex_t *, pAbc->pGia->pCexComb, pTemp->pCexComb );
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Gia_ManStop( pTemp );
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// handle the case when the output is disproved by an all-0 primary input pattern
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ABC_FREE( pAbc->pGia->pCexComb );
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Gia_ManSetPhase( pAbc->pGia );
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Gia_ManForEachCo( pAbc->pGia, pObj, i )
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if ( pObj->fPhase )
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{
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pAbc->pGia->pCexComb = Abc_CexAlloc( 0, Gia_ManCiNum(pAbc->pGia), 1 );
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if ( !pPars->fSilent )
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{
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Abc_Print( 1, "Networks are NOT EQUIVALENT. Output %d trivially differs (different phase). ", i );
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Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
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}
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break;
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}
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if ( pAbc->pGia->pCexComb == NULL )
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{
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Gia_Man_t * pTemp = Gia_ManDemiterToDual( pAbc->pGia );
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pAbc->Status = Cec_ManVerify( pTemp, pPars );
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ABC_SWAP( Abc_Cex_t *, pAbc->pGia->pCexComb, pTemp->pCexComb );
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Gia_ManStop( pTemp );
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}
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}
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Abc_FrameReplaceCex( pAbc, &pAbc->pGia->pCexComb );
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return 0;
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