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Passing node labels.

This commit is contained in:
Alan Mishchenko 2021-04-26 18:52:44 -07:00
parent 75981f7fee
commit de71e5f610
3 changed files with 10 additions and 0 deletions
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1
src/base/abc/abcObj.c
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@ -393,6 +393,7 @@ Abc_Obj_t * Abc_NtkDupObj( Abc_Ntk_t * pNtkNew, Abc_Obj_t * pObj, int fCopyName
}
else if ( Abc_ObjIsLatch(pObj) ) // copy the reset value
pObjNew->pData = pObj->pData;
pObjNew->fPersist = pObj->fPersist;
// transfer HAIG
// pObjNew->pEquiv = pObj->pEquiv;
// remember the new node in the old node

1
src/base/abci/abcDar.c
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@ -858,6 +858,7 @@ Abc_Ntk_t * Abc_NtkFromMappedGia( Gia_Man_t * p, int fFindEnables, int fUseBuffs
Gia_LutForEachFanin( p, i, iFan, k )
Abc_ObjAddFanin( pObjNew, Abc_NtkObj(pNtkNew, Gia_ObjValue(Gia_ManObj(p, iFan))) );
pObjNew->pData = Abc_ObjHopFromGia( (Hop_Man_t *)pNtkNew->pManFunc, p, i, vReflect );
pObjNew->fPersist = Gia_ObjLutIsMux(p, i);
pObj->Value = Abc_ObjId( pObjNew );
}
Vec_PtrFree( vReflect );

8
src/base/io/ioWriteVerilog.c
View File

@ -567,6 +567,14 @@ void Io_WriteVerilogObjects( FILE * pFile, Abc_Ntk_t * pNtk, int fOnlyAnds )
Hop_IthVar((Hop_Man_t *)pNtk->pManFunc, k)->pData = Extra_UtilStrsav(Io_WriteVerilogGetName(Abc_ObjName(pFanin)));
// write the formula
Hop_ObjPrintVerilog( pFile, pFunc, vLevels, 0, fOnlyAnds );
if ( pObj->fPersist )
{
Abc_Obj_t * pFan0 = Abc_ObjFanin0(Abc_ObjFanin(pObj, 0));
Abc_Obj_t * pFan1 = Abc_ObjFanin0(Abc_ObjFanin(pObj, 1));
int Cond = Abc_ObjIsNode(pFan0) && Abc_ObjIsNode(pFan1) && !pFan0->fPersist && !pFan1->fPersist;
fprintf( pFile, "; // MUXF7 %s\n", Cond ? "":"to be legalized" );
}
else
fprintf( pFile, ";\n" );
// clear the input names
Abc_ObjForEachFanin( pObj, pFanin, k )