mirror of https://github.com/YosysHQ/abc.git
Adding an option to write Verilog with LUT instances.
This commit is contained in:
Alan Mishchenko
parent
73f8b598ac
commit
f9af41ba1b
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@ -2982,14 +2982,27 @@ usage:
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***********************************************************************/
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int IoCommandWriteVerilog( Abc_Frame_t * pAbc, int argc, char **argv )
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{
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extern void Io_WriteVerilogLut( Abc_Ntk_t * pNtk, char * pFileName, int nLutSize );
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char * pFileName;
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int c, fOnlyAnds = 0;
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int nLutSize = -1;
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Extra_UtilGetoptReset();
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while ( ( c = Extra_UtilGetopt( argc, argv, "ah" ) ) != EOF )
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while ( ( c = Extra_UtilGetopt( argc, argv, "Kah" ) ) != EOF )
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{
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switch ( c )
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{
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case 'K':
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if ( globalUtilOptind >= argc )
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{
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Abc_Print( -1, "Command line switch \"-K\" should be followed by an integer.\n" );
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goto usage;
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}
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nLutSize = atoi(argv[globalUtilOptind]);
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globalUtilOptind++;
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if ( nLutSize < 2 || nLutSize > 6 )
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goto usage;
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break;
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case 'a':
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fOnlyAnds ^= 1;
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break;
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@ -3017,13 +3030,16 @@ int IoCommandWriteVerilog( Abc_Frame_t * pAbc, int argc, char **argv )
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Io_WriteVerilog( pNtkTemp, pFileName, 1 );
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Abc_NtkDelete( pNtkTemp );
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}
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else if ( nLutSize >= 2 && nLutSize <= 6 )
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Io_WriteVerilogLut( pAbc->pNtkCur, pFileName, nLutSize );
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else
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Io_Write( pAbc->pNtkCur, pFileName, IO_FILE_VERILOG );
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Io_Write( pAbc->pNtkCur, pFileName, IO_FILE_VERILOG );
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return 0;
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usage:
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fprintf( pAbc->Err, "usage: write_verilog [-ah] <file>\n" );
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fprintf( pAbc->Err, "usage: write_verilog [-K num] [-ah] <file>\n" );
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fprintf( pAbc->Err, "\t writes the current network in Verilog format\n" );
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fprintf( pAbc->Err, "\t-K num : write the network using instances of K-LUTs (2 <= K <= %d) [default = not used]\n", 6, nLutSize );
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fprintf( pAbc->Err, "\t-a : toggle writing expressions with only ANDs (without XORs and MUXes) [default = %s]\n", fOnlyAnds? "yes":"no" );
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fprintf( pAbc->Err, "\t-h : print the help massage\n" );
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fprintf( pAbc->Err, "\tfile : the name of the file to write\n" );
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@ -653,6 +653,183 @@ char * Io_WriteVerilogGetName( char * pName )
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return Buffer;
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}
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/**Function*************************************************************
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Synopsis [Write the network of K-input LUTs.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Io_WriteLutModule( FILE * pFile, int nLutSize )
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{
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fprintf( pFile, "module lut%d #( parameter TT = %d\'h0 ) ( input [%d:0] in, output out );\n", nLutSize, 1<<nLutSize, nLutSize-1 );
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fprintf( pFile, " assign out = TT[in];\n" );
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fprintf( pFile, "endmodule\n\n" );
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}
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void Io_WriteVerilogObjectsLut( FILE * pFile, Abc_Ntk_t * pNtk, int nLutSize )
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{
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Abc_Ntk_t * pNtkBox;
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Abc_Obj_t * pObj, * pTerm;
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int i, k, Counter, nDigits, Length = 0;
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// write boxes
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nDigits = Abc_Base10Log( Abc_NtkBoxNum(pNtk)-Abc_NtkLatchNum(pNtk) );
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Counter = 0;
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Abc_NtkForEachBox( pNtk, pObj, i )
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{
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if ( Abc_ObjIsLatch(pObj) )
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continue;
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pNtkBox = (Abc_Ntk_t *)pObj->pData;
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fprintf( pFile, " %s box%0*d", pNtkBox->pName, nDigits, Counter++ );
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fprintf( pFile, "(" );
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Abc_NtkForEachPi( pNtkBox, pTerm, k )
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{
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fprintf( pFile, ".%s", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(pTerm))) );
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fprintf( pFile, "(%s), ", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanin0(Abc_ObjFanin(pObj,k)))) );
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}
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Abc_NtkForEachPo( pNtkBox, pTerm, k )
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{
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fprintf( pFile, ".%s", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanin0(pTerm))) );
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fprintf( pFile, "(%s)%s", Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(Abc_ObjFanout(pObj,k)))), k==Abc_NtkPoNum(pNtkBox)-1? "":", " );
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}
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fprintf( pFile, ");\n" );
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}
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// find the longest signal name
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Abc_NtkForEachNode( pNtk, pObj, i )
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{
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Length = Abc_MaxInt( Length, strlen(Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(pObj)))) );
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Abc_ObjForEachFanin( pObj, pTerm, k )
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Length = Abc_MaxInt( Length, strlen(Io_WriteVerilogGetName(Abc_ObjName(pTerm))) );
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}
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// write LUT instances
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nDigits = Abc_Base10Log( Abc_NtkNodeNum(pNtk) );
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Counter = 0;
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Abc_NtkForEachNode( pNtk, pObj, i )
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{
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word Truth = Abc_SopToTruth( (char *)pObj->pData, Abc_ObjFaninNum(pObj) );
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fprintf( pFile, " lut%d #(%d\'h", nLutSize, 1<<nLutSize );
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if ( nLutSize == 6 )
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fprintf( pFile, "%08x%08x", (unsigned)(Truth >> 32), (unsigned)Truth );
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else
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fprintf( pFile, "%0*x", 1<<(nLutSize-2), Abc_InfoMask(1 << nLutSize) & Truth );
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fprintf( pFile, ") lut_%0*d ( {", nDigits, Counter++ );
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for ( k = nLutSize - 1; k >= Abc_ObjFaninNum(pObj); k-- )
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fprintf( pFile, "%*s, ", Length, "1\'b0" );
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for ( k = Abc_ObjFaninNum(pObj) - 1; k >= 0; k-- )
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fprintf( pFile, "%*s%s", Length, Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanin(pObj, k))), k==0 ? "":", " );
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fprintf( pFile, "}, %*s );\n", Length, Io_WriteVerilogGetName(Abc_ObjName(Abc_ObjFanout0(pObj))) );
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}
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}
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void Io_WriteVerilogLutInt( FILE * pFile, Abc_Ntk_t * pNtk, int nLutSize )
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{
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// write inputs and outputs
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// fprintf( pFile, "module %s ( gclk,\n ", Abc_NtkName(pNtk) );
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fprintf( pFile, "module %s ( ", Io_WriteVerilogGetName(Abc_NtkName(pNtk)) );
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// add the clock signal if it does not exist
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if ( Abc_NtkLatchNum(pNtk) > 0 && Nm_ManFindIdByName(pNtk->pManName, "clock", ABC_OBJ_PI) == -1 )
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fprintf( pFile, "clock, " );
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// write other primary inputs
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fprintf( pFile, "\n " );
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if ( Abc_NtkPiNum(pNtk) > 0 )
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{
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Io_WriteVerilogPis( pFile, pNtk, 3 );
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fprintf( pFile, ",\n " );
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}
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if ( Abc_NtkPoNum(pNtk) > 0 )
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Io_WriteVerilogPos( pFile, pNtk, 3 );
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fprintf( pFile, " );\n\n" );
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// add the clock signal if it does not exist
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if ( Abc_NtkLatchNum(pNtk) > 0 && Nm_ManFindIdByName(pNtk->pManName, "clock", ABC_OBJ_PI) == -1 )
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fprintf( pFile, " input clock;\n" );
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// write inputs, outputs, registers, and wires
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if ( Abc_NtkPiNum(pNtk) > 0 )
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{
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// fprintf( pFile, " input gclk," );
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fprintf( pFile, " input " );
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Io_WriteVerilogPis( pFile, pNtk, 10 );
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fprintf( pFile, ";\n" );
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}
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if ( Abc_NtkPoNum(pNtk) > 0 )
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{
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fprintf( pFile, " output" );
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Io_WriteVerilogPos( pFile, pNtk, 5 );
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fprintf( pFile, ";\n\n" );
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}
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// if this is not a blackbox, write internal signals
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if ( !Abc_NtkHasBlackbox(pNtk) )
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{
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if ( Abc_NtkLatchNum(pNtk) > 0 )
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{
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fprintf( pFile, " reg" );
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Io_WriteVerilogRegs( pFile, pNtk, 4 );
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fprintf( pFile, ";\n\n" );
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}
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if ( Io_WriteVerilogWiresCount(pNtk) > 0 )
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{
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fprintf( pFile, " wire" );
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Io_WriteVerilogWires( pFile, pNtk, 4 );
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fprintf( pFile, ";\n\n" );
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}
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// write nodes
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Io_WriteVerilogObjectsLut( pFile, pNtk, nLutSize );
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// write registers
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if ( Abc_NtkLatchNum(pNtk) > 0 )
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{
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fprintf( pFile, "\n" );
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Io_WriteVerilogLatches( pFile, pNtk );
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}
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}
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// finalize the file
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fprintf( pFile, "\nendmodule\n\n" );
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}
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void Io_WriteVerilogLut( Abc_Ntk_t * pNtk, char * pFileName, int nLutSize )
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{
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FILE * pFile;
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Abc_Ntk_t * pNtkTemp;
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Abc_Obj_t * pObj;
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int i, Counter = 0;
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Abc_NtkForEachNode( pNtk, pObj, i )
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if ( Abc_ObjFaninNum(pObj) > nLutSize )
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{
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if ( Counter < 3 )
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printf( "Node \"%s\" has the fanin count (%d) larger than the LUT size (%d).\n", Abc_ObjName(pObj), Abc_ObjFaninNum(pObj), nLutSize );
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Counter++;
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}
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if ( Counter )
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{
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printf( "In total, %d internal logic nodes exceeded the fanout count limit.\n", Counter );
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return;
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}
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// start the output stream
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pFile = fopen( pFileName, "w" );
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if ( pFile == NULL )
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{
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fprintf( stdout, "Io_WriteVerilog(): Cannot open the output file \"%s\".\n", pFileName );
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return;
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}
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// write the equations for the network
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fprintf( pFile, "// Benchmark \"%s\" written by ABC on %s\n", pNtk->pName, Extra_TimeStamp() );
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fprintf( pFile, "\n" );
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Io_WriteLutModule( pFile, nLutSize );
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pNtkTemp = Abc_NtkToNetlist( pNtk );
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Abc_NtkToSop( pNtkTemp, -1, ABC_INFINITY );
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Io_WriteVerilogLutInt( pFile, pNtkTemp, nLutSize );
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Abc_NtkDelete( pNtkTemp );
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fprintf( pFile, "\n" );
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fclose( pFile );
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}
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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