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Several changes for standard mapping.

This commit is contained in:
Alan Mishchenko 2021-04-28 00:11:02 -07:00
parent 5f8a8a596a
commit 9b75906740
3 changed files with 18 additions and 5 deletions
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6
src/base/abci/abc.c
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@ -29886,8 +29886,10 @@ static inline int Abc_NtkCompareWithBest( Abc_Ntk_t * pBest, Abc_Ntk_t * p,
Abc_NtkPoNum(pBest) != Abc_NtkPoNum(p) ||
Abc_NtkLatchNum(pBest) != Abc_NtkLatchNum(p) ||
strcmp(Abc_NtkName(pBest), Abc_NtkName(p)) ||
(!fArea && (*pnBestNtkLevels > nNtkLevels || (*pnBestNtkLevels == nNtkLevels && *pnBestNtkDelay > nNtkDelay ))) ||
( fArea && (*pnBestNtkNodes > nNtkNodes || (*pnBestNtkNodes == nNtkNodes && *pnBestNtkArea > nNtkArea )))
// (!fArea && (*pnBestNtkLevels > nNtkLevels || (*pnBestNtkLevels == nNtkLevels && *pnBestNtkDelay > nNtkDelay ))) ||
// ( fArea && (*pnBestNtkNodes > nNtkNodes || (*pnBestNtkNodes == nNtkNodes && *pnBestNtkArea > nNtkArea )))
(!fArea && (*pnBestNtkDelay > nNtkDelay || (*pnBestNtkDelay == nNtkDelay && *pnBestNtkArea > nNtkArea ))) ||
( fArea && (*pnBestNtkArea > nNtkArea || (*pnBestNtkArea == nNtkArea && *pnBestNtkDelay > nNtkDelay )))
)
{
*pnBestNtkArea = nNtkArea;

15
src/map/scl/scl.c
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@ -153,11 +153,12 @@ int Scl_CommandReadLib( Abc_Frame_t * pAbc, int argc, char ** argv )
float Gain = 0;
int nGatesMin = 0;
int fShortNames = 0;
int fUnit = 0;
int fVerbose = 1;
int fVeryVerbose = 0;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "SGMdnvwh" ) ) != EOF )
while ( ( c = Extra_UtilGetopt( argc, argv, "SGMdnuvwh" ) ) != EOF )
{
switch ( c )
{
@ -200,6 +201,9 @@ int Scl_CommandReadLib( Abc_Frame_t * pAbc, int argc, char ** argv )
case 'n':
fShortNames ^= 1;
break;
case 'u':
fUnit ^= 1;
break;
case 'v':
fVerbose ^= 1;
break;
@ -242,6 +246,12 @@ int Scl_CommandReadLib( Abc_Frame_t * pAbc, int argc, char ** argv )
// dump the resulting library
if ( fDump && pAbc->pLibScl )
Abc_SclWriteLiberty( Extra_FileNameGenericAppend(pFileName, "_temp.lib"), (SC_Lib *)pAbc->pLibScl );
if ( fUnit )
{
SC_Cell * pCell; int i;
SC_LibForEachCell( pLib, pCell, i )
pCell->area = 1;
}
// extract genlib library
if ( pAbc->pLibScl )
{
@ -251,13 +261,14 @@ int Scl_CommandReadLib( Abc_Frame_t * pAbc, int argc, char ** argv )
return 0;
usage:
fprintf( pAbc->Err, "usage: read_lib [-SG float] [-M num] [-dnvwh] <file>\n" );
fprintf( pAbc->Err, "usage: read_lib [-SG float] [-M num] [-dnuvwh] <file>\n" );
fprintf( pAbc->Err, "\t reads Liberty library from file\n" );
fprintf( pAbc->Err, "\t-S float : the slew parameter used to generate the library [default = %.2f]\n", Slew );
fprintf( pAbc->Err, "\t-G float : the gain parameter used to generate the library [default = %.2f]\n", Gain );
fprintf( pAbc->Err, "\t-M num : skip gate classes whose size is less than this [default = %d]\n", nGatesMin );
fprintf( pAbc->Err, "\t-d : toggle dumping the parsed library into file \"*_temp.lib\" [default = %s]\n", fDump? "yes": "no" );
fprintf( pAbc->Err, "\t-n : toggle replacing gate/pin names by short strings [default = %s]\n", fShortNames? "yes": "no" );
fprintf( pAbc->Err, "\t-u : toggle setting unit area for all cells [default = %s]\n", fUnit? "yes": "no" );
fprintf( pAbc->Err, "\t-v : toggle writing verbose information [default = %s]\n", fVerbose? "yes": "no" );
fprintf( pAbc->Err, "\t-w : toggle writing information about skipped gates [default = %s]\n", fVeryVerbose? "yes": "no" );
fprintf( pAbc->Err, "\t-h : prints the command summary\n" );

2
src/proof/cec/cecSim.c
View File

@ -328,7 +328,7 @@ int Cec_ManSRunSim( Cec_ManS_t * p, int iNode0, int iNode1 )
{
abctime clk = Abc_Clock();
//Vec_Int_t * vLevel;
int pNodes[2] = { iNode0, iNode1 };
//int pNodes[2] = { iNode0, iNode1 };
int i, iNode, Status, fDiff = Gia_ObjPhaseDiff( p->pAig, iNode0, iNode1 );
word * pSim00 = Cec_ManSSim( p, iNode0, 0 );
word * pSim01 = Cec_ManSSim( p, iNode0, 1 );