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1,467 Commits 27 Branches 57 Tags 58 MiB
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172 Commits

Author SHA1 Message Date
Alan Mishchenko d261e617fc Added command to transform GIA into the file with truth tables for each output. 2012-10-10 01:11:24 -07:00
Alan Mishchenko 4ed89d00fe Making explicit cast to 64-bit unsigned in a few places. 2012-10-09 09:23:08 -07:00
Alan Mishchenko 56d3d7cd22 C++ portability changes. 2012-10-03 21:49:18 -07:00
Alan Mishchenko 71bdfae941 Replacing 'st_table' by 'st__table' to resolve linker problems. 2012-09-29 17:11:03 -04:00
Alan Mishchenko aed3b3a13a Cleaned up interfaces of genlib/liberty/supergate reading/writing. 2012-09-25 01:34:26 -07:00
Alan Mishchenko d0197d8378 Changed printouts in a few places in supergate computation. 2012-09-24 22:57:01 -07:00
Alan Mishchenko 5f09917c22 Added simplification before the concurrent call to PDR. 2012-09-20 19:51:39 -07:00
Alan Mishchenko 266af49386 Modified 'read' to read all types of libraries (genlib, liberty, scl). 2012-09-20 13:12:51 -07:00
Alan Mishchenko bc44087bac Modified 'read' to read all types of libraries (genlib, liberty, scl). 2012-09-20 12:41:59 -07:00
Alan Mishchenko f59de3decc Fixes to Verilog parser. 2012-09-20 11:29:37 -07:00
Alan Mishchenko 5dc50744f0 Extending Liberty parser to handle multi-output cells. 2012-09-19 18:42:00 -07:00
Alan Mishchenko 480ca14c75 Extending Liberty parser to handle multi-output cells. 2012-09-19 17:35:04 -07:00
Alan Mishchenko 3af0f719af Extending BLIF parser/write to hangle multi-output cells. 2012-09-19 16:28:06 -07:00
Alan Mishchenko 69bbfa9856 Created new abstraction package from the code that was all over the place. 2012-09-15 23:27:46 -07:00
Alan Mishchenko a246882a5b Scalable gate-level abstraction. 2012-09-11 19:11:51 -07:00
Alan Mishchenko 784a3579e5 Fixing Verilog writer's way of writing module names. 2012-09-11 18:44:07 -07:00
Alan Mishchenko a49ba2d280 Fixing the way constants are written into mapped Verilog files. 2012-08-31 00:05:10 -07:00
Alan Mishchenko 1c33107cbb Updating project settings to have simpler include paths. 2012-07-07 20:14:12 -07:00
Alan Mishchenko ea98a2497e Fixing time primtouts throughout the code. 2012-07-07 18:41:02 -07:00
Alan Mishchenko 3aab724573 Fixing time primtouts throughout the code. 2012-07-07 17:46:54 -07:00
Alan Mishchenko bea33c0584 Diabling compact AIGER writing by default. 2012-07-07 12:23:03 -07:00
Alan Mishchenko e908ff1cb9 Improving printouts of critical path. 2012-04-09 11:46:42 -07:00
Alan Mishchenko aede5026b3 Silencing a gcc warning. 2012-03-23 22:55:45 -07:00
Alan Mishchenko 0792ab0eb6 Additional features for delay optimization 2012-03-21 23:19:49 -07:00
Alan Mishchenko c46c957a07 Renamed Aig_ObjIsPi/Po to be ...Ci/Co and Aig_Man(Pi/Po)Num to be ...(Ci/Co)... 2012-03-09 19:50:18 -08:00
Alan Mishchenko 2c8f1a67ec Renamed Aig_ManForEachPi/Po to be ...Ci/Co and Aig_ObjCreatePi/Po to be ...Ci/Co. 2012-03-09 19:32:44 -08:00
Alan Mishchenko eb4aa42577 Enabling user-specified required times in 'map'. 2012-03-02 13:50:28 -08:00
Alan Mishchenko 97856d021a Silencing some of the gcc warnings. 2012-02-16 23:40:23 -08:00
Alan Mishchenko 791b107e7a Silencing some of the gcc warnings. 2012-02-16 21:53:16 -08:00
Alan Mishchenko c5067f7d04 Graph isomorphism checking code. 2012-02-11 00:22:05 -08:00
Alan Mishchenko 8014f25f6d Major restructuring of the code. 2012-01-21 04:30:10 -08:00
Alan Mishchenko 8c62c9db6c Added switch 'write_counter -f' to output flop values in each time frame. 2012-01-18 17:49:13 -08:00
Alan Mishchenko ac7e665bf6 Bug fixes in the Verilog parser. 2012-01-14 22:21:23 -08:00
Alan Mishchenko 5fff8354ce New hierarchy manager. 2012-01-13 22:02:04 -08:00
Alan Mishchenko 26b87c8c55 Added warning when the network from file has no primary inputs. 2012-01-06 01:36:08 +07:00
Alan Mishchenko 82a2495ce9 Improvements to hierarchical BLIF parser. 2011-12-22 14:26:03 -08:00
Alan Mishchenko b3c9609e82 Improvements to hierarchical BLIF parser. 2011-12-21 12:56:28 -08:00
Alan Mishchenko 3418a8820a Fixed a bug in matching code. 2011-12-17 17:51:13 -08:00
Alan Mishchenko beb29257bf Added support for generating a library of real-life truth-tables. 2011-12-09 00:38:16 -08:00
Alan Mishchenko 200c5cc659 Added support for generating a library of real-life truth-tables. 2011-12-09 00:37:05 -08:00
Alan Mishchenko 30ea50a3b4 Temporary debugging change. 2011-11-12 23:21:41 -08:00
Alan Mishchenko 3beb36778e Enabled counter-example minimization in 'write_counter'. 2011-11-11 20:56:05 -08:00
Alan Mishchenko 0b73c76380 Preventing scripts from aborting if reading has failed. 2011-11-08 17:58:51 -08:00
Alan Mishchenko d2ced9f82e Changes to read multi-output testcases described using AIGER 1.9. 2011-11-06 23:15:27 -08:00
Alan Mishchenko f08be2742e C++ portability changes. 2011-10-27 23:34:11 -07:00
Alan Mishchenko 12b70d4946 Changes to CNF generation code. 2011-10-17 10:39:05 +03:00
Alan Mishchenko ad5ee9ff46 Changes to the matching procedure. 2011-10-12 15:04:41 +03:00
Alan Mishchenko d66b586330 Modified write_blif to output LUT structures. 2011-10-04 18:43:23 +07:00
Alan Mishchenko 94726c981b Other changes to enable new features in the mapper (bug fix). 2011-08-06 13:28:22 +08:00
Alan Mishchenko b9dea5d674 Other changes to enable new features in the mapper (bug fix). 2011-08-06 01:31:07 +08:00