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3073 Commits

Author SHA1 Message Date
Ethan Mahintorabi b7c7a6d98d
Fixes duplicate declaration of Abc_SclHasDelayInfo 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-02 02:15:59 +00:00
William D. Jones 402c2579db Modify include guards in cmd.c so that Windows compilers don't compile Unix-only code. 2024-04-27 19:06:36 -04:00
aletempiac 043a2ffcc6 Adding new XX decomposition to &if 2024-04-23 11:10:16 +02:00
Alan Mishchenko c14d5f3906 Dumping miter statistics. 2024-04-22 22:06:07 -04:00
Martin Povišer e6a3dc602c Fix prototype mismatch for `Gia_ManSimRsb` 2024-04-22 17:34:38 +02:00
aletempiac 864f96b11e Adding decomposition of mapping into LUT structures before returning the result 2024-04-16 17:40:47 +02:00
aletempiac 045803dcb8 Merge remote-tracking branch 'origin/master' into acd66 2024-04-11 19:02:29 +02:00
aletempiac 6052d10fde Adding new command if -U for 2-LUT decompositions under delay profile 2024-04-11 15:45:37 +02:00
aletempiac 32bc1d4ab2 Cleaning and generalizing code 2024-04-11 11:31:28 +02:00
Alan Mishchenko 6e1653426f Switch to randomly select one choice. 2024-03-28 16:22:06 +08:00
Alan Mishchenko a2cb5eb4e3 Adding command &pms to print miter status. 2024-03-25 23:39:03 +08:00
Alan Mishchenko b0d2ff1c63 Exact synthesis using NAND-gates. 2024-03-24 00:10:08 +09:00
aletempiac db72df7a63 Merge remote-tracking branch 'origin/master' into acd66 2024-03-18 10:08:48 +01:00
alanminko 3040b8ddd5
Merge pull request #282 from allen1236/master 
&brecover with speculative reduction
 2024-03-16 08:52:57 +09:00
Allen Ho b7884aaf2b clean up & add options for &brecover 2024-03-16 01:40:11 +08:00
Allen Ho 015dd2a367 use speculative in &brecover 2024-03-15 16:56:10 +08:00
Alan Mishchenko a16a0f1027 Writing Verilog for AIG using NAND gates. 2024-03-06 01:40:48 -08:00
Allen Ho bfbec71211 &stc_eco and &brecover done 2024-03-04 09:36:35 +08:00
Allen Ho bcf04fadb6 &brecover done 2024-03-04 00:54:23 +08:00
alanminko 390a0e8ef3
Merge pull request #279 from allen1236/master 
Sat-sweeping-based ECO (&str_eco)
 2024-03-02 15:38:08 -08:00
Allen Ho 23654254e1 clean up 2024-03-03 03:06:13 +08:00
Allen Ho f5f4dca013 clean up 2024-03-02 21:08:10 +08:00
aletempiac 9bec2afd60 Removing -z flag to execute delay-driven ACD 2024-03-01 10:04:48 +01:00
Allen Ho 6f5656c188 shared EI/EO not handled yet 2024-03-01 16:05:41 +08:00
Alan Mishchenko 1fd79c8430 Fixing a bug in input/output name ordering. 2024-02-29 15:19:47 -08:00
aletempiac f72000f5ae Adding ACD cascade 666, performance improvements 2024-02-21 18:25:48 +01:00
aletempiac 17afd93c78 Extending ACD to work up to 11 variables 2024-02-08 15:36:09 +01:00
aletempiac 2d9af6c9a4 Adding ACD for 66 LUT structure using a new method 2024-02-08 09:36:58 +01:00
Alan Mishchenko 52e0a10bf7 Fixing a compiler problem. 2024-02-05 20:49:36 -08:00
Alan Mishchenko e9a0bf6bf9 Adding reversing of simulation bits in &sim_read. 2024-02-05 20:32:11 -08:00
Alan Mishchenko 62a22c7574 Bug fix in blasting multipliers with different argument bit-width. 2024-02-05 19:26:36 -08:00
Allen Ho c74144c6eb str_eco ver1 2024-02-01 07:25:46 +08:00
Alan Mishchenko 6d1d52deaa Adding an option to read the RTL elaboration library from the current directory. 2024-01-30 20:22:55 -08:00
Alan Mishchenko d6555f48dd Adding a switch to not write the timestamp in the AIGER file. 2024-01-26 07:31:20 -08:00
Alan Mishchenko 8da884de85 Switch to reverse the order of bits. 2024-01-18 18:23:11 -08:00
Baruch Sterin 234af64a8c Workaround for C++17 compilation (on clang) 2024-01-18 09:58:18 -08:00
aletempiac d223898f3d Merge remote-tracking branch 'origin/master' into acd 2024-01-16 17:44:45 +01:00
Alan Mishchenko dc68fe27f9 Saving module interface. 2024-01-11 19:45:42 -08:00
Alan Mishchenko 5978ccdb52 Updating sleep command to wait for file. 2023-12-21 12:16:33 +09:00
Alan Mishchenko 7fe92148cc New command to put computation to sleep. 2023-12-18 21:04:31 +09:00
Allen Ho 284b9d6a9c extended box report; 2023-12-10 21:30:46 +08:00
Allen Ho 9bb5333f62 extend bo 2023-12-07 19:07:52 +08:00
aletempiac b3d2419d9a Formatting, renaming, and cleaning code 2023-11-27 13:38:36 +01:00
aletempiac 1d7dfd25c6 Improving ACD mapping 2023-11-17 16:58:17 +01:00
aletempiac 1632dc0d4e First version of ACD 2023-11-15 18:38:00 +01:00
Alan Mishchenko 6ca7eab466 Prototype of integrating decomposition into "if". 2023-11-14 12:58:03 -08:00
Alan Mishchenko eb264c5d22 Suggested fixes. 2023-11-13 17:19:54 -08:00
WWFUG 67a2b97cf0 added -I options in &bmiter 2023-11-08 19:00:03 +08:00
Alan Mishchenko 5de12aa6b3 Experiments with SAT solving. 2023-10-23 11:30:44 -07:00
Alan Mishchenko 76e8d21aaf Printout changes. 2023-10-23 10:48:43 -07:00
Alan Mishchenko 01ad71b26f Experiments with verification. 2023-10-23 09:38:08 -07:00
Alan Mishchenko 8dbf8965fd Adding batch option to "scrgen". 2023-10-23 09:37:04 -07:00
Alan Mishchenko 652a0aaef7 Compiler warning. 2023-10-20 22:42:40 -07:00
Alan Mishchenko 72b423ba14 Experiments with SAT solving. 2023-10-20 20:53:43 -07:00
wjrforcyber c2fdb86a4d Refactor(Typo): Typo in ACD 2023-10-07 13:53:22 +08:00
wjrforcyber fb6a4722c2 Merge remote-tracking branch 'upstream/master' into typo 2023-10-07 13:50:29 +08:00
Alan Mishchenko 3c4c558656 Experiment with script generation. 2023-10-02 16:47:37 -07:00
Alan Mishchenko 65ccd3cc69 Enabled literal remapping. 2023-09-29 16:07:29 -07:00
Alan Mishchenko cc636a0d83 Experiments with verification. 2023-09-28 06:40:57 -07:00
wjrforcyber ecf6255985 Refactor(Typo):Missing a parameter fUseLutLib and use fSaveBest twice 2023-09-26 14:24:02 +08:00
wjrforcyber 3781c1df61 Refactor(Typo): Link is NOT FOUND page(not available), change to the book name 2023-09-24 19:31:37 +08:00
Alan Mishchenko 4d1618f600 Enable dumping Verilog with assign-statements. 2023-09-21 11:08:43 +08:00
Allen Ho 31ad17fa1a add abc9RecoverBoundary 2023-09-20 14:23:47 +08:00
Alan Mishchenko 7fd4b01fb3 Automatic script file generation. 2023-09-18 16:30:09 +08:00
Alan Mishchenko 09b0295c1a Adding aliases for some commands. 2023-09-18 16:27:54 +08:00
wjrforcyber eae19f7a62 Refactor(Typo): Typo in strash 2023-09-18 13:56:18 +08:00
wjrforcyber 05c897a753 Refactor(Typo): Typo in read_aiger 2023-09-17 19:34:56 +08:00
wjrforcyber e1db615384 Merge branch 'master' into typo 2023-09-17 13:28:57 +08:00
wjrforcyber 7ec8f17094 Refactor(Typo): Typo update in write_aiger message 2023-09-17 13:27:00 +08:00
Alan Mishchenko 9399faac48 Improvements to &gen_hie. 2023-09-17 12:40:33 +08:00
Alan Mishchenko 2f5b81119b Experiments with retiming. 2023-09-17 12:17:27 +08:00
wjrforcyber 136bae27d8 Refactor(Typo): Typo update in read_aiger comment 2023-09-16 19:43:03 +08:00
Alan Mishchenko 475c8dad8e Compiler problem. 2023-09-16 07:13:10 +08:00
Cunxi Yu 1261f71248
Merge branch 'berkeley-abc:master' into master 2023-09-15 13:25:27 -07:00
Alan Mishchenko 57cc2bd089 Compiler problem. 2023-09-15 22:51:11 +08:00
Alan Mishchenko 09013f3a6e New command &gen_hie to generate hierarchical designs. 2023-09-15 22:44:31 +08:00
Alan Mishchenko 1ffdbbbebe Corner-case bug fix. 2023-09-11 10:46:38 +07:00
Alan Mishchenko 588122dc72 Writing an interface module when dumping Verilog. 2023-09-11 09:44:22 +07:00
Alan Mishchenko a4755a37cb Experiments with CEC. 2023-09-08 22:42:41 +07:00
Alan Mishchenko f844fb1057 Command to add one flop to the design. 2023-09-08 16:46:14 +07:00
Alan Mishchenko 0c719ab69e Adding procedure to merge two libraries. 2023-09-08 14:23:14 +07:00
alanminko 00fa1e3714
Merge pull request #241 from wjrforcyber/typo 
Refactor(Typo):Typo currently exists
 2023-09-05 14:09:40 +07:00
alanminko 4c718f7b50
Merge pull request #218 from seccipon/master 
1. Fix bug (using pDesign without check if == NULL) 2. Switch type of variables containing file size to (int => long)
 2023-09-05 14:08:51 +07:00
alanminko 7f22cc07b8
Merge pull request #194 from jamesjer/badfile 
Do not pass NULL to fprintf
 2023-09-05 14:07:35 +07:00
alanminko 1cd5a2ce04
Merge pull request #156 from Teemperor/FixMemoryLeak 
Fix some memory leaks
 2023-09-05 14:05:09 +07:00
alanminko 3daa630a03
Merge pull request #242 from DanielG/spelling-fixes 
treewide: Fix spelling mistakes
 2023-09-05 13:31:50 +07:00
Alan Mishchenko 167fceac37 Enabling command history on Linux. 2023-09-05 11:11:18 +07:00
Alan Mishchenko a13dae7a4a Corner-case bug in truth table reading. 2023-09-04 08:18:02 +07:00
wjrforcyber 1a525c57a6 Merge remote-tracking branch 'upstream/master' into typo 2023-08-29 10:57:06 +08:00
wjrforcyber b8f5708ec1 Refactor(Typo):Expends->Expands 2023-08-29 10:46:57 +08:00
Cunxi Yu 3488a35472
Merge branch 'berkeley-abc:master' into master 2023-08-27 10:21:43 -07:00
CUNXI YU 855976c61d correct the naming of augmentation 2023-08-27 11:19:26 -06:00
CUNXI YU 0fe977a33c correct the naming of augmentation 2023-08-27 11:18:35 -06:00
Daniel Gröber b7d1435db1 treewide: Fix spelling mistakes 
A particularly pedantic set of changes currently used in Debian

Authored-By: Ruben Undheim <ruben.undheim@gmail.com>
 2023-08-27 14:13:20 +02:00
Alan Mishchenko 3309ccabd4 Cleaning up AIG output in EQN format. 2023-08-26 17:12:50 +07:00
wjrforcyber 0971429b56 Refactor(Typo):rec_add2 is no longer exist 2023-08-18 12:42:13 +08:00
lyj1201 0fab82384a add AIG random synthesis based RTL argumentation; command = aigarg 2023-08-14 12:04:33 -06:00
Alan Mishchenko c4839c92a8 Fixing 'read_truth' to read a constant truth table 2023-08-14 21:21:02 +07:00
Alan Mishchenko 42683a7370 Fixed performance bug in Feb 28 commit (0d0063f). 2023-08-12 16:36:18 +07:00
Alan Mishchenko a7aa3deac9 Fixed a corner-case bug in Aug 5 commit (3daecc0). 2023-08-12 16:32:56 +07:00
Alan Mishchenko a603186d8e "Fixing usage message of &ps." 2023-08-11 07:14:11 +07:00
alanminko e387ddf849
Merge pull request #236 from MyskYko/fix_rwr 
update reverse level when co is replaced
 2023-08-06 08:52:20 +07:00
MyskYko 3daecc0ea8 update reverse level when co is replaced 2023-08-05 13:35:41 -07:00
Alan Mishchenko 039f05cb56 Adding preprocessing to command &splitsat. 2023-07-27 20:50:02 -07:00
Alan Mishchenko 74157fc0ab New command &splitsat. 2023-07-27 16:00:17 -07:00
Alan Mishchenko 19eaa55c2a Experiments with cube ordering. 2023-07-23 10:14:35 -07:00
Alan Mishchenko 683882f2bb Experiments with stochastic synthesis. 2023-07-22 22:18:28 -07:00
Alan Mishchenko 0108175c6c Bug fix in 'dsd'. 2023-07-22 17:08:01 -07:00
Alan Mishchenko a620c09c40 Adding functional comparison to &compare. 2023-07-22 16:44:33 -07:00
Alan Mishchenko 3592078ddb Partitioned &scorr. 2023-07-21 18:49:06 -07:00
Alan Mishchenko 55ed1e6698 Changing command &permute to generate random NPNP transformations. 2023-07-21 16:15:34 -07:00
Alan Mishchenko 623d0f3c9f Change in how signal names are printing in 'print_level'. 2023-07-18 21:00:13 -07:00
Alan Mishchenko 0828ac28a0 Bug fix in Verilog writer. 2023-07-18 15:53:20 -07:00
Alan Mishchenko 59cfcd2240 Compiler warnings. 2023-07-18 09:00:11 -07:00
Cunxi Yu 5bb7fb76a7 add orchestration function (local greedy); usage: orchestrate -h 2023-07-16 12:20:10 -06:00
Alan Mishchenko c70de10002 Updating &saveaig command. 2023-07-14 20:06:22 -07:00
Alan Mishchenko 373c5eccf3 Experiment with multipliers. 2023-07-07 13:12:22 -07:00
alanminko 3d35624be6
Merge pull request #224 from MyskYko/transduction 
Transduction option fix and multi-threading
 2023-05-14 14:12:26 -07:00
Yukio Miyasaka 16894c56ee thread parallelism 2023-05-14 13:48:40 -07:00
Alan Mishchenko bb4378934d Removing a global variable in resub. 2023-05-13 13:53:59 -07:00
Yukio Miyasaka 3af039d7c3 zero cost hop 2023-05-12 22:10:40 -07:00
Yukio Miyasaka a3fb930e44 fix option 2023-05-12 21:44:29 -07:00
alanminko 41a2b2a0ef
Merge pull request #223 from MyskYko/transduction 
transtoch with exdc
 2023-05-12 12:36:05 -07:00
MyskYko 1f16d8bc90 transtoch with exdc 2023-05-12 12:15:23 -07:00
alanminko 233680f286
Merge pull request #220 from MyskYko/transduction 
Stochastic Transduction Script
 2023-05-10 12:09:45 -07:00
MyskYko 36b357175a stochastic script for transduction 2023-05-06 04:15:34 -07:00
alanminko 38cd47b46c
Merge pull request #219 from MyskYko/transduction 
Transduction method
 2023-05-04 14:20:34 -04:00
MyskYko 3b946e76e3 options 2023-05-04 02:12:58 -07:00
MyskYko 920f4dbb7d verbose 2023-05-04 01:49:30 -07:00
MyskYko ec626957b5 option change 2023-05-03 10:46:42 -07:00
MyskYko 6e985705fc transduction 2023-05-02 16:48:33 -07:00
Andrey Rogov d785775f64 1. Fix bug (using pDesign without check if == NULL) 
2. Switch type of variables containing file size to (int => long)
 2023-04-28 01:52:01 +03:00
Alan Mishchenko 65a756bf01 Command to write the network into an edgelist file, contributed by Cunxi Yu (University of Utah). 2023-04-25 12:58:59 -04:00
Alan Mishchenko 1a91797316 Trying to fix a spurious build error. 2023-04-22 19:17:56 -07:00
Alan Mishchenko b633363f06 Trying to fix a spurious build error. 2023-04-04 10:43:01 +08:00
Alan Mishchenko 36a83acf3c Experiments with sequential mapping. 2023-03-31 19:52:46 +07:00
Alan Mishchenko 1229d1ff07 New options to print out sim info. 2023-03-16 13:03:07 +07:00
Alan Mishchenko 6d9c8daece Fix duplicating invs/bufs driving primary outputs in 'write_verilog'. 2023-03-11 22:28:38 +07:00
Alan Mishchenko 8ffb7811c7 New options to print out sim info (warning). 2023-03-11 20:35:23 +07:00
Alan Mishchenko 7bc6f3396e New options to print out sim info. 2023-03-11 20:25:11 +07:00
Alan Mishchenko 953970e73a Skipping zero partial products. 2023-03-05 11:42:26 +07:00
Alan Mishchenko 9d0e828b85 Fixing compiler error. 2023-03-01 19:12:06 +07:00
Alan Mishchenko 3370370101 Adding switch 'show -d' to keep (not delete) the .dot file after generating the .ps file. 2023-03-01 19:00:44 +07:00
Alan Mishchenko a79dc18eb2 Enabling generation of non-restoring divider. 2023-03-01 18:41:24 +07:00
alanminko 91aaff2575 More compiler warnings. 2023-02-28 03:07:41 -08:00
Alan Mishchenko 667326b18e Compiler warnings. 2023-02-28 15:53:12 +07:00
Alan Mishchenko 622d142794 Compiler warnings. 2023-02-28 15:40:06 +07:00
Alan Mishchenko b57b546494 Compiler warnings. 2023-02-28 15:16:31 +07:00
Alan Mishchenko 0d0063f7de Experiment with cost functions. 2023-02-28 13:50:35 +07:00
Alan Mishchenko 581c58b9c4 Experiment with choice computation. 2023-02-16 07:14:18 +01:00