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Skipping zero partial products.

This commit is contained in:
Alan Mishchenko 2023-03-05 11:42:26 +07:00
parent 9d0e828b85
commit 953970e73a
2 changed files with 23 additions and 13 deletions
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15
src/base/wlc/wlcBlast.c
View File

@ -1131,13 +1131,14 @@ void Wlc_BlastBooth( Gia_Man_t * pNew, int * pArgA, int * pArgB, int nArgA, int
int This = i == nArgA ? FillA : pArgA[i];
int Prev = i ? pArgA[i-1] : 0;
int Part = Gia_ManHashOr( pNew, Gia_ManHashAnd(pNew, One, This), Gia_ManHashAnd(pNew, Two, Prev) );
pp = Gia_ManHashXor( pNew, Part, Neg );
if ( pp == 0 || (fSigned && i == nArgA) )
continue;
Vec_WecPush( vProds, k+i, pp );
Vec_WecPush( vLevels, k+i, 0 );
if ( pp )
{
Vec_WecPush( vProds, k+i, pp );
Vec_WecPush( vLevels, k+i, 0 );
}
}
if ( fSigned ) i--;
// perform sign extension
@ -1150,13 +1151,19 @@ void Wlc_BlastBooth( Gia_Man_t * pNew, int * pArgA, int * pArgB, int nArgA, int
Vec_WecPush( vProds, k+i+1, Sign );
Vec_WecPush( vLevels, k+i+1, 0 );
if ( Sign != 1 )
{
Vec_WecPush( vProds, k+i+2, Abc_LitNot(Sign) );
Vec_WecPush( vLevels, k+i+2, 0 );
}
}
else
{
if ( Sign != 1 )
{
Vec_WecPush( vProds, k+i, Abc_LitNot(Sign) );
Vec_WecPush( vLevels, k+i, 0 );
}
Vec_WecPush( vProds, k+i+1, 1 );
Vec_WecPush( vLevels, k+i+1, 0 );

21
src/base/wln/wlnRtl.c
View File

@ -143,13 +143,15 @@ Rtl_Lib_t * Wln_ReadSystemVerilog( char * pFileName, char * pTopModule, char * p
int fSVlog = strstr(pFileName, ".sv") != NULL;
if ( strstr(pFileName, ".rtl") )
return Rtl_LibReadFile( pFileName, pFileName );
sprintf( Command, "%s -qp \"read_verilog %s %s%s; hierarchy %s%s; %sproc; write_rtlil %s\"",
sprintf( Command, "%s -qp \"read_verilog %s%s %s%s; hierarchy %s%s; %sproc; write_rtlil %s\"",
Wln_GetYosysName(),
pDefines ? pDefines : "",
fSVlog ? "-sv ":"", pFileName,
pDefines ? "-D" : "",
pDefines ? pDefines : "",
fSVlog ? "-sv " : "",
pFileName,
pTopModule ? "-top " : "",
pTopModule ? pTopModule : "",
fCollapse ? "flatten; " : "",
fCollapse ? "flatten; ": "",
pFileTemp );
if ( fVerbose )
printf( "%s\n", Command );
@ -172,13 +174,14 @@ Gia_Man_t * Wln_BlastSystemVerilog( char * pFileName, char * pTopModule, char *
char * pFileTemp = "_temp_.aig";
int fRtlil = strstr(pFileName, ".rtl") != NULL;
int fSVlog = strstr(pFileName, ".sv") != NULL;
sprintf( Command, "%s -qp \"%s %s%s%s; hierarchy %s%s; flatten; proc; %saigmap; write_aiger %s\"",
sprintf( Command, "%s -qp \"%s %s%s %s%s; hierarchy %s%s; flatten; proc; %saigmap; write_aiger %s\"",
Wln_GetYosysName(),
fRtlil ? "read_rtlil" : "read_verilog",
fRtlil ? "read_rtlil" : "read_verilog",
pDefines ? "-D" : "",
pDefines ? pDefines : "",
fSVlog ? " -sv ":" ",
pFileName,
pTopModule ? "-top " : "-auto-top",
fSVlog ? "-sv " : "",
pFileName,
pTopModule ? "-top " : "-auto-top",
pTopModule ? pTopModule : "",
fTechMap ? "techmap; setundef -zero; " : "", pFileTemp );
if ( fVerbose )