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3073 Commits

Author SHA1 Message Date
wjrforcyber 17652cfda6
Feat(write_hmetis): Write out hMetis file format 2024-12-25 15:37:36 +08:00
Alan Mishchenko 733fec328c Fixing big-endian problems in mfs2 and &mfs. 2024-12-23 20:04:21 -08:00
Alan Mishchenko e21399f3bc Compiler warning. 2024-12-23 08:55:59 -08:00
alanminko 01c6102ca7
Merge pull request #350 from wjrforcyber/put_bug_on_choice 
Fix(&put): &put bug with choices
 2024-12-23 08:52:29 -08:00
alanminko 733d2cd390
Merge pull request #348 from wjrforcyber/mem_leak 
Refactor(MemLeak): MemLeak fix in orchestrate
 2024-12-23 08:52:12 -08:00
Alan Mishchenko 207cfddaa8 Experiments with structural LUT cascade mapping. 2024-12-21 21:24:45 -08:00
Carmine50 b999084ade [CEC][SimGen][CLI] Removed option of nMaxStep since it was unused 2024-12-19 18:12:28 +01:00
Carmine50 30af6f9868 [CEC][SimGen][CLI] Change name of command for simgen 2024-12-19 17:25:45 +01:00
Carmine50 91dcfae020 [CEC][SimGen][Experiment ID] Added experiment ID option to test different experiments with simgen 2024-12-18 19:56:12 +01:00
Carmine50 cbd4456805 [CEC][SimGen][Experiment ID] Added experiment ID option to test different experiments with simgen 2024-12-18 19:53:44 +01:00
Carmine50 99648e132f [CEC][SimGen][CLI] Added command line function to call SimGen main function. 2024-12-18 18:43:38 +01:00
wjrforcyber a8c65f1343
Fix(&put): &put bug with choices 
Related: #349
 2024-12-17 14:05:58 +08:00
Alan Mishchenko 8ba3d9b91c Trying anothe resource limit in scorr. 2024-12-14 13:44:18 -08:00
wjrforcyber 7391a297bb
Refactor(MemLeak): MemLeak fix in orchestrate 2024-12-06 18:13:32 +08:00
Ethan Mahintorabi 01c9a65a47
map: Add Mio_Library_t* parameter to Abc_NtkMap 
This lets users of the ABC API call map without relying on the static
Mio_Library_t* in Abc_FrameReadLibGen.
 2024-12-02 06:55:42 +00:00
Alan Mishchenko 14168eb509 Updating command "rungen" to generate random functions. 2024-11-27 22:01:27 -08:00
Alan Mishchenko 1f3cf0aad9 Experiment with "scorr". 2024-11-17 15:44:32 -08:00
Alan Mishchenko 3aff0af0c5 Adding command for generating sorters. 2024-11-11 21:02:59 -08:00
Alan Mishchenko aeb977286f Updates to LUT cascade synthesis. 2024-11-10 18:54:35 -08:00
Alan Mishchenko c787e32f86 Adding postiive minterm count for random functions generated by "lutexact". 2024-11-05 22:01:07 -08:00
Alan Mishchenko 091ff4e7a9 Adding generation of random functions to "lutexact" 2024-11-05 19:23:04 -08:00
Alan Mishchenko ecd948027e Fixing assertion failures in &put. 2024-10-23 14:49:57 +07:00
alanminko 743f3a7bdd
Merge pull request #250 from wjrforcyber/typo 
Refactor(Typo):Typo currently exists
 2024-10-21 01:54:12 -07:00
Alan Mishchenko 2e3384390a Updating "lutexact" to run on symmetric functions. 2024-10-07 14:10:02 +07:00
Alan Mishchenko af1de4fa9c Improved bit-blasting of some word-level operators. 2024-10-01 20:34:58 +07:00
Alan Mishchenko a78d358e1c Extending &funtrace to dump and load precomputed library. 2024-10-01 20:33:01 +07:00
Alan Mishchenko 6004b7b21e Adding API for inserting danginling flop. 2024-10-01 15:55:45 +07:00
Alan Mishchenko 9c152b71e9 Trasferring equivalence in the special-case usage of &scorr. 2024-09-12 18:11:59 -07:00
Alan Mishchenko 0d10253bd0 Another way of writing primary outputs in Verilog. 2024-09-06 06:27:53 -07:00
Alan Mishchenko 03d92930fa Updating &funtrace to trace function of the primary outputs of the AIG. 2024-09-03 17:16:48 -07:00
wjrforcyber 252afb1521
Refactor(Resub): Clear mark A/B 2024-08-28 16:51:33 +08:00
wjrforcyber bcf292fdeb
Refactor(Resub): Clear markB at the beginning 2024-08-28 15:41:09 +08:00
Alan Mishchenko 03b786af99 Experiments with adder-based circuits. 2024-08-17 16:26:20 -07:00
Alan Mishchenko 2055b1b490 Adding an option to dump satisfying assignments into a BLIF file. 2024-08-14 14:41:35 -07:00
Alan Mishchenko c099e62032 Adding a switch to complement the primary outputs of an AIG. 2024-08-14 13:40:52 -07:00
Alan Mishchenko 1a62954eb8 Adding command to read ROM data. 2024-08-14 12:56:10 -07:00
Alan Mishchenko e2b7750d3b Experiments with bit-blasting. 2024-08-14 11:40:41 -07:00
alanminko 324ceeaa08
Merge pull request #320 from YosysHQ/povik/revert-pdr 
Revert recent PDR changes
 2024-08-12 17:17:24 -07:00
Alan Mishchenko 81fcf8494e Updating "lutexact" to support single-rail LUT cascade. 2024-08-12 16:26:55 -07:00
Martin Povišer de8620d777 Revert "pdr -X to write CEXes immediately" 
This reverts commit e62e8ac528.
 2024-08-12 22:53:53 +02:00
Martin Povišer ec8419c84b Revert "Improved anytime pdr" 
This reverts commit 5444cf281c.
 2024-08-12 22:53:40 +02:00
Alan Mishchenko e824cca0ca Fixing a serious bug in bit-blasting when multiplier argments have different bit-width. 2024-08-10 19:13:50 -07:00
Alan Mishchenko 35a1bbbdb4 Ongoing development related to Boolean decomposition. 2024-08-09 18:33:36 -07:00
Alan Mishchenko 4156a88dbb Extending &funtrace to trace functions found in an AIG. 2024-08-09 12:39:43 -07:00
alanminko 0129b4c60a
Merge pull request #316 from YosysHQ/povik/yosyshq-commands 
Pull command changes from YosysHQ fork
 2024-08-08 14:59:31 -07:00
alanminko e6b36cb5da
Merge pull request #315 from YosysHQ/povik/yosyshq-build 
Pull build-related changes from YosysHQ fork
 2024-08-08 14:58:42 -07:00
Alan Mishchenko 95f1837960 Ongoing development related to Boolean decomposition. 2024-08-07 10:07:39 -07:00
Jannis Harder 5444cf281c Improved anytime pdr 
(cherry picked from commit c832967200)
 2024-08-07 15:46:44 +02:00
Jannis Harder e62e8ac528 pdr -X to write CEXes immediately 
(cherry picked from commit f63471bdf5)
 2024-08-07 15:46:44 +02:00
Martin Povišer 1383c76464 Pull YosysHQ read_cex/write_cex changes 
See

 - YosysHQ/abc#19
 - YosysHQ/abc#16
 - commit 6234e18d
 - YosysHQ/abc#14
 - YosysHQ/abc#12
 - YosysHQ/abc#11

Co-authored-by: Jannis Harder <me@jix.one>
Co-authored-by: Claire Xenia Wolf <claire@clairexen.net>
Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
 2024-08-07 15:46:43 +02:00