AngeloJacobo
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47766cb8e8
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added wishbone 2 and formally verified it
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2023-07-13 18:41:25 +08:00 |
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AngeloJacobo
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5904a4910d
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shortened formal depth from 9 to 7
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2023-07-09 09:34:03 +08:00 |
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AngeloJacobo
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b03ca1864f
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shortened formal depth from 17 to 9
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2023-07-08 10:19:58 +08:00 |
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AngeloJacobo
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b3c9bdb650
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pass test for timing params with depth of 9
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2023-07-06 20:29:50 +08:00 |
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AngeloJacobo
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10c290f9f8
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temp newest version
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2023-07-05 19:46:18 +08:00 |
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AngeloJacobo
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3250d8d368
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write dqs toggles for half slow clk cycle at the end, needed when DQ is set to be delayed (non-zero flyby delay)
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2023-07-05 16:41:55 +08:00 |
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AngeloJacobo
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ce3ca7e158
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pre-refresh delay is now flexible and not fixed. Separated formal properties for testing time parameters
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2023-07-05 16:35:57 +08:00 |
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AngeloJacobo
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217770b977
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verified precharge and activate cmds, fixed bug in write_calib cmd
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2023-07-02 06:38:33 +08:00 |
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AngeloJacobo
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188b26ee12
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assume no request when slave busy (calibration or at refresh)
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2023-06-29 12:58:41 +08:00 |
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AngeloJacobo
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760c75d238
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passes optimized pipeline stall control and passed fwb_slave properties
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2023-06-29 12:56:24 +08:00 |
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AngeloJacobo
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2cfbba6d28
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change ff to unix
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2023-06-24 08:04:21 +08:00 |
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AngeloJacobo
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2221a739db
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add 2 clocks in prestall delay to pass tWR violation, add more asserts for fwb_slave
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2023-06-24 07:46:09 +08:00 |
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AngeloJacobo
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b0e3b83e96
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added wb properties from zipcpu repo
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2023-06-22 19:54:39 +08:00 |
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AngeloJacobo
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ef10bfd455
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add data mask port
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2023-06-22 19:52:45 +08:00 |
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AngeloJacobo
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272711762e
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add phy for data mask (oserdes -> odelay -> obuf)
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2023-06-22 19:51:06 +08:00 |
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AngeloJacobo
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0ffdacf6e7
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add logic for write wb_ack, wb_sel, and aux
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2023-06-22 19:49:05 +08:00 |
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AngeloJacobo
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0923fdc0b6
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add formal assertions using fifo to prove every wb request has a corresponding read/write command output
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2023-06-15 17:43:15 +08:00 |
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AngeloJacobo
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053a511144
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set write-to-read delay for all banks for every write
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2023-06-10 08:19:16 +08:00 |
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AngeloJacobo
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806b49ebd5
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changed folder name with underscore
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2023-06-08 14:05:35 +08:00 |
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AngeloJacobo
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f3e15e9ea4
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added test 1: Sequential write then sequential read
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2023-06-08 13:56:54 +08:00 |
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AngeloJacobo
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2e6c2183aa
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added sim duration for possible bus delays
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2023-06-08 13:55:20 +08:00 |
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AngeloJacobo
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de37c5a972
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added wires for loadingg delay tap
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2023-06-08 13:53:07 +08:00 |
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AngeloJacobo
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b9204332b1
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made delay tap loadable
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2023-06-08 13:52:04 +08:00 |
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AngeloJacobo
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c3707dab53
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made delay tap loadable and made delay more flexible to use all 32 taps for both dqs and dq
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2023-06-08 11:01:56 +08:00 |
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Angelo Jacobo
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98ed92a65b
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added testbench for a single ddr3 device sim
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2023-06-03 14:28:55 +08:00 |
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Angelo Jacobo
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9a19f82377
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added testbench for model simulation
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2023-06-03 14:24:11 +08:00 |
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Angelo Jacobo
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884fd2bcad
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Add files via upload
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2023-06-01 19:59:45 +08:00 |
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Angelo Jacobo
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6127bba77a
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fixed data alignment for write operation, fixed CL and CWL for 100MHz:400MHz clk
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2023-06-01 19:18:41 +08:00 |
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Angelo Jacobo
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26af4960e9
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fixed display for prev_cmd and time difference
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2023-06-01 19:15:36 +08:00 |
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Angelo Jacobo
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0a43b04f9e
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added phy for generating differential o_ddr3_clk
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2023-05-29 21:51:48 +08:00 |
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Angelo Jacobo
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d6b6c0b9a4
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added o_ddr3_clk port
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2023-05-29 21:48:44 +08:00 |
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Angelo Jacobo
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9e529131c0
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fixed error "added_read_pipe has multiple drivers"
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2023-05-29 20:52:48 +08:00 |
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Angelo Jacobo
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a56e6a8a24
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changed write calibration pattern with high autocorrel stat
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2023-05-29 16:40:41 +08:00 |
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Angelo Jacobo
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400a277cdc
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added 52ns sync reset (IDELAYCTRL requirement)
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2023-05-29 16:19:32 +08:00 |
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Angelo Jacobo
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02d512df55
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Delete sdram.txt
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2023-05-28 16:20:52 +08:00 |
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Angelo Jacobo
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12b533a9d1
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added top module which instantiates the controller and phy
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2023-05-28 16:20:22 +08:00 |
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Angelo Jacobo
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f648035e4e
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added phy interface (separated from controller)
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2023-05-28 16:19:47 +08:00 |
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Angelo Jacobo
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ab26902f7a
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include only the controller (phy is now a separate module)
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2023-05-28 16:18:14 +08:00 |
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Angelo Jacobo
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854839dde9
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readme file from Micron
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2023-05-28 16:14:21 +08:00 |
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Angelo Jacobo
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b9154a38bb
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Delete rtl/DDR3 directory
clean-up the repo
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2023-05-28 16:11:49 +08:00 |
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Angelo Jacobo
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fb8dd029e3
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Delete ug586_7Series_MIS.pdf
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2023-05-28 16:08:40 +08:00 |
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Angelo Jacobo
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6710b5b62b
|
Add files via upload
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2023-05-25 19:14:12 +08:00 |
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Angelo Jacobo
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1e89a236df
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fixed implementation errors in Vivado
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2023-05-25 19:13:30 +08:00 |
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Angelo Jacobo
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a7de749ddf
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Add files via upload
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2023-05-22 19:53:20 +08:00 |
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Angelo Jacobo
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94d6253069
|
Add files via upload
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2023-05-18 11:02:40 +08:00 |
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Angelo Jacobo
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991dcad40b
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Add files via upload
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2023-05-18 10:50:30 +08:00 |
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Angelo Jacobo
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8e6c422689
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complete read and write calibration
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2023-05-18 10:45:26 +08:00 |
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Angelo Jacobo
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c33bc40bd3
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Update ddr3_controller.v
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2023-05-11 15:35:34 +08:00 |
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Angelo Jacobo
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9be5b5a616
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Update ddr3_controller.v
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2023-05-11 14:49:47 +08:00 |
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Angelo Jacobo
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f3c4b1b465
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Update ddr3_controller.v
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2023-05-10 15:23:48 +08:00 |