Commit Graph

145 Commits

Author SHA1 Message Date
AngeloJacobo 89c2b8fbd7 set depth to 7 (minimum) 2023-07-13 18:43:47 +08:00
AngeloJacobo 47766cb8e8 added wishbone 2 and formally verified it 2023-07-13 18:41:25 +08:00
AngeloJacobo 5904a4910d shortened formal depth from 9 to 7 2023-07-09 09:34:03 +08:00
AngeloJacobo b03ca1864f shortened formal depth from 17 to 9 2023-07-08 10:19:58 +08:00
AngeloJacobo 25d7f3bffd update gtkw 2023-07-06 20:33:48 +08:00
AngeloJacobo a4d4e3a099 change all to non-blocking 2023-07-06 20:32:12 +08:00
AngeloJacobo b3c9bdb650 pass test for timing params with depth of 9 2023-07-06 20:29:50 +08:00
AngeloJacobo 69c34dbf8f update logs 2023-07-05 19:48:14 +08:00
AngeloJacobo 1881e059bc add summary log of regression test (not yet complete) 2023-07-05 19:47:00 +08:00
AngeloJacobo 10c290f9f8 temp newest version 2023-07-05 19:46:18 +08:00
AngeloJacobo 122e2a2d3c exported simulation scripts from Vivado 2023-07-05 16:50:40 +08:00
AngeloJacobo ec6488f68f gtkw for testing time parameters 2023-07-05 16:48:40 +08:00
AngeloJacobo ab17b8012b add average rate in report 2023-07-05 16:44:31 +08:00
AngeloJacobo 7af3358162 update vivado wcfg file 2023-07-05 16:42:48 +08:00
AngeloJacobo 3250d8d368 write dqs toggles for half slow clk cycle at the end, needed when DQ is set to be delayed (non-zero flyby delay) 2023-07-05 16:41:55 +08:00
AngeloJacobo ce3ca7e158 pre-refresh delay is now flexible and not fixed. Separated formal properties for testing time parameters 2023-07-05 16:35:57 +08:00
AngeloJacobo 217770b977 verified precharge and activate cmds, fixed bug in write_calib cmd 2023-07-02 06:38:33 +08:00
AngeloJacobo 3c32501ffd log before passing fwb_slave 2023-06-29 19:37:49 +08:00
AngeloJacobo bf7f9142b8 log after passing fwb_slave 2023-06-29 19:24:06 +08:00
AngeloJacobo d6f9614295 update gtkw 2023-06-29 13:03:08 +08:00
AngeloJacobo 3251dda112 added gtkw for cover 2023-06-29 13:00:52 +08:00
AngeloJacobo ba00cb9063 changed to non-blocking simulation 2023-06-29 12:59:57 +08:00
AngeloJacobo 188b26ee12 assume no request when slave busy (calibration or at refresh) 2023-06-29 12:58:41 +08:00
AngeloJacobo 2ca5a15c30 add cover 2023-06-29 12:56:58 +08:00
AngeloJacobo 760c75d238 passes optimized pipeline stall control and passed fwb_slave properties 2023-06-29 12:56:24 +08:00
AngeloJacobo 463707a07c sim log before passing fwb_slave 2023-06-28 21:16:56 +08:00
AngeloJacobo 2cfbba6d28 change ff to unix 2023-06-24 08:04:21 +08:00
AngeloJacobo 6f90bc165c passes all test with no violations 2023-06-24 07:59:05 +08:00
AngeloJacobo 4ecf119454 add error injections and use aux to determine ack request type 2023-06-24 07:56:05 +08:00
AngeloJacobo c9e29935a0 add more pins in gtkw 2023-06-24 07:54:17 +08:00
AngeloJacobo 310f2d5af8 update wcfg 2023-06-24 07:53:28 +08:00
AngeloJacobo a42a13ecab Merge branch 'main' of https://github.com/AngeloJacobo/DDR3_Controller into main 2023-06-24 07:52:02 +08:00
AngeloJacobo 2221a739db add 2 clocks in prestall delay to pass tWR violation, add more asserts for fwb_slave 2023-06-24 07:46:09 +08:00
Angelo Jacobo e97dae7d5b
Update README.md 2023-06-22 20:01:01 +08:00
AngeloJacobo b0e3b83e96 added wb properties from zipcpu repo 2023-06-22 19:54:39 +08:00
AngeloJacobo d93cf9fb4e fixed delay for data mask as same delay as dq 2023-06-22 19:53:37 +08:00
AngeloJacobo ef10bfd455 add data mask port 2023-06-22 19:52:45 +08:00
AngeloJacobo 272711762e add phy for data mask (oserdes -> odelay -> obuf) 2023-06-22 19:51:06 +08:00
AngeloJacobo 0ffdacf6e7 add logic for write wb_ack, wb_sel, and aux 2023-06-22 19:49:05 +08:00
AngeloJacobo f4b138ff77 Merge branch 'main' of https://github.com/AngeloJacobo/DDR3_Controller into main 2023-06-22 19:45:16 +08:00
AngeloJacobo 96f4edd3e8 add wb properties module 2023-06-22 19:44:37 +08:00
Angelo Jacobo 4cb3b4a4b5
Update README.md 2023-06-15 18:54:42 +08:00
Angelo Jacobo 4786c77176
Update temp.log 2023-06-15 18:52:08 +08:00
AngeloJacobo a98364dd1e added gtkw for formal 2023-06-15 17:46:58 +08:00
AngeloJacobo 1937d34565 create test 1(sequential access to first,middle,last rows) and test 2(random access) 2023-06-15 17:46:14 +08:00
AngeloJacobo 0923fdc0b6 add formal assertions using fifo to prove every wb request has a corresponding read/write command output 2023-06-15 17:43:15 +08:00
AngeloJacobo fd897b76bb update size of command_used 2023-06-15 17:33:09 +08:00
AngeloJacobo 7c8b8af71f add minimum depth requirement for possible clock periods 2023-06-15 17:24:48 +08:00
AngeloJacobo 60c9d5ae85 added command type to be displayed in ASCII, changed all to posedge 2023-06-10 08:41:37 +08:00
AngeloJacobo acedb1310b added delay counters for debugging 2023-06-10 08:40:13 +08:00