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Angelo Jacobo
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################################################################################
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##
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## Filename: sdram.txt
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## {{{
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## Project: 10Gb Ethernet switch
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##
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## Purpose: To describe how to provide access to an SDRAM controller
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## from the Wishbone bus, where such SDRAM controller uses a
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## different clock from the Wishbone bus itself.
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##
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## Creator: Dan Gisselquist, Ph.D.
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## Gisselquist Technology, LLC
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##
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################################################################################
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## }}}
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## Copyright (C) 2023, Gisselquist Technology, LLC
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## {{{
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## This file is part of the ETH10G project.
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##
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## The ETH10G project contains free software and gateware, licensed under the
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## Apache License, Version 2.0 (the "License"). You may not use this project,
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## or this file, except in compliance with the License. You may obtain a copy
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## of the License at
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## }}}
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## http://www.apache.org/licenses/LICENSE-2.0
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## {{{
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## Unless required by applicable law or agreed to in writing, files
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## distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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## WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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## License for the specific language governing permissions and limitations
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## under the License.
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##
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################################################################################
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##
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## }}}
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@PREFIX=sdram
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@DEVID=SDRAM
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@ACCESS=@$(DEVID)_ACCESS
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@DEPENDS=ALLCLOCKS_PRESENT
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## LGMEMSZ is the size of the SDRAM in bytes, 29 => 512MB
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@$LGMEMSZ=29
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@LGMEMSZ.FORMAT=%d
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@$UNUSED=9
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@$NADDR=(1<<(LGMEMSZ-(@$(UNUSED))))
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@$NBYTES=(1<<(@$LGMEMSZ))
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@NBYTES.FORMAT=0x%08x
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@$MADDR= @$(REGBASE)
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@MADDR.FORMAT=0x%08x
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@SLAVE.TYPE=MEMORY
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@SLAVE.BUS=wbwide
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# @CLOCK.NAME=clk
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# @CLOCK.FREQUENCY = 81250000
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@BUS=wbwide
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## @ERROR.WIRE=@$(PREFIX)_err
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# 8-bit byte accesses
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@$ABITS=@$(LGMEMSZ)-@$(UNUSED)
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@LD.PERM=wx
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@TOP.PORTLIST=
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// SDRAM I/O port wires
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o_ddr3_reset_n, o_ddr3_cke_n, o_ddr3_clk_p, o_ddr3_clk_n,
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o_ddr3_ras_n, o_ddr3_cas_n, o_ddr3_we_n,
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io_ddr3_dqs_p, io_ddr3_dqs_n,
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o_ddr3_a, o_ddr3_ba,
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io_ddr3_dq, o_ddr3_dm, o_ddr3_odt
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@TOP.IODECL=
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// I/O declarations for the DDR3 SDRAM
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// {{{
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output wire o_ddr3_reset_n;
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output wire [0:0] o_ddr3_cke_n;
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output wire [0:0] o_ddr3_clk_p, o_ddr3_clk_n;
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//output wire [0:0] ddr3_cs_n; // This design has no CS pin
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output wire o_ddr3_ras_n, o_ddr3_cas_n, o_ddr3_we_n;
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output wire [2:0] o_ddr3_ba;
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output wire [14:0] o_ddr3_a;
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output wire [0:0] o_ddr3_odt;
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output wire [7:0] o_ddr3_dm;
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inout wire [7:0] io_ddr3_dqs_p, io_ddr3_dqs_n;
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inout wire [63:0] io_ddr3_dq;
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// }}}
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@TOP.DEFNS=
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// Wires necessary to run the SDRAM
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// {{{
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wire @$(PREFIX)_cyc, @$(PREFIX)_stb, @$(PREFIX)_we,
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@$(PREFIX)_stall, @$(PREFIX)_ack, @$(PREFIX)_err;
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wire [(@$(LGMEMSZ)-@$(UNUSED)-1):0] @$(PREFIX)_addr;
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wire [(@$(BUS.WIDTH)-1):0] @$(PREFIX)_wdata,
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@$(PREFIX)_rdata;
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wire [(@$(BUS.WIDTH)/8-1):0] @$(PREFIX)_sel;
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// }}}
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// Wires coming back from the SDRAM
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//wire s_clk, s_reset;
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@TOP.MAIN=
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// The SDRAM interface to an toplevel AXI4 module
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//
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@$(PREFIX)_cyc, @$(PREFIX)_stb, @$(PREFIX)_we,
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@$(PREFIX)_addr, @$(PREFIX)_wdata, @$(PREFIX)_sel,
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@$(PREFIX)_stall, @$(PREFIX)_ack, @$(PREFIX)_rdata,
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@$(PREFIX)_err
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@TOP.INSERT=
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wire [31:0] @$(PREFIX)_debug;
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ddr3_controller @$(PREFIX)i(
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// {{{
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// clock and reset
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.i_controller_clk(s_clk200),
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.i_ddr3_clk(s_clk200), //200MHz input clock
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.i_rst_n(s_reset),
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// Wishbone inputs
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.i_wb_cyc(@$(PREFIX)_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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.i_wb_stb(@$(PREFIX)_stb), //request a transfer
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.i_wb_we(@$(PREFIX)_we), //write-enable (1 = write, 0 = read)
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.i_wb_addr(@$(PREFIX)_addr), //burst-addressable {row,bank,col}
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.i_wb_data(@$(PREFIX)_wdata), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
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.i_wb_sel(@$(PREFIX)_sel), //byte strobe for write (1 = write the byte)
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.i_aux(), //for AXI-interface compatibility (given upon strobe)
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// Wishbone outputs
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.o_wb_stall(@$(PREFIX)_stall), //1 = busy, cannot accept requests
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.o_wb_ack(@$(PREFIX)_ack), //1 = read/write request has completed
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.o_wb_data(@$(PREFIX)_rdata), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
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.o_aux(), //for AXI-interface compatibility (returned upon ack)
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// PHY Interface
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.ck_en(o_ddr3_cke_n), // CKE
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.cs_n(), // chip select signal
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.odt(o_ddr3_odt), // on-die termination
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.ras_n(o_ddr3_ras_n), // RAS#
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.cas_n(o_ddr3_cas_n), // CAS#
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.we_n(o_ddr3_we_n), // WE#
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.reset_n(o_ddr3_reset_n),
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.addr(o_ddr3_a),
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.ba_addr(o_ddr3_ba),
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.dq(io_ddr3_dq),
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.dqs(io_ddr3_dqs_p),
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.dqs_n(io_ddr3_dqs_n)
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// }}}
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);
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@MAIN.PORTLIST=
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// SDRAM ports
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o_@$(PREFIX)_cyc, o_@$(PREFIX)_stb, o_@$(PREFIX)_we,
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o_@$(PREFIX)_addr, o_@$(PREFIX)_data, o_@$(PREFIX)_sel,
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i_@$(PREFIX)_stall, i_@$(PREFIX)_ack, i_@$(PREFIX)_data,
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i_@$(PREFIX)_err
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@MAIN.IODECL=
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// SDRAM I/O declarations
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// {{{
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output wire o_@$(PREFIX)_cyc,
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o_@$(PREFIX)_stb, o_@$(PREFIX)_we;
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output wire [@$(ABITS)-1:0] o_@$(PREFIX)_addr;
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output wire [(@$(BUS.WIDTH)-1):0] o_@$(PREFIX)_data;
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output wire [(@$(BUS.WIDTH)/8)-1:0] o_@$(PREFIX)_sel;
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//
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input wire i_@$(PREFIX)_ack;
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input wire i_@$(PREFIX)_stall;
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input wire [(@$(BUS.WIDTH)-1):0] i_@$(PREFIX)_data;
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// Verilator lint_off UNUSED
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input wire i_@$(PREFIX)_err;
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// Verilator lint_on UNUSED
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// }}}
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@MAIN.INSERT=
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////////////////////////////////////////////////////////////////////////
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//
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// Export the @$(PREFIX) bus to the top level
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// {{{
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assign o_@$(PREFIX)_cyc = @$(SLAVE.PREFIX)_cyc;
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assign o_@$(PREFIX)_stb =(@$(SLAVE.PREFIX)_stb);
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assign o_@$(PREFIX)_we = @$(SLAVE.PREFIX)_we;
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assign o_@$(PREFIX)_addr = @$(SLAVE.PREFIX)_addr[@$(ABITS)-1:0];
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assign o_@$(PREFIX)_data = @$(SLAVE.PREFIX)_data;
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assign o_@$(PREFIX)_sel = @$(SLAVE.PREFIX)_sel;
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assign @$(SLAVE.PREFIX)_ack = i_@$(PREFIX)_ack;
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assign @$(SLAVE.PREFIX)_stall = i_@$(PREFIX)_stall;
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assign @$(SLAVE.PREFIX)_idata = i_@$(PREFIX)_data;
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// }}}
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@REGS.N=1
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@REGS.0= 0 R_@$(DEVID) @$(DEVID)
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@REGDEFS.H.DEFNS=
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#define @$(DEVID)BASE @$[0x%08x](REGBASE)
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#define @$(DEVID)LEN @$(NBYTES)
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@BDEF.OSDEF=_BOARD_HAS_@$(DEVID)
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@BDEF.OSVAL=extern char _@$(PREFIX)[@$NBYTES];
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@LD.PERM=wx
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@SIM.INCLUDE=
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#include "memsim.h"
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@SIM.DEFNS=
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#ifdef @$(ACCESS)
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MEMSIM *m_@$(PREFIX);
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#endif // @$(ACCESS)
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@SIM.INIT=
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#ifdef @$(ACCESS)
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m_@$(PREFIX) = new MEMSIM(@$(NBYTES));
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#endif // @$(ACCESS)
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@SIM.CLOCK=@$(SLAVE.BUS.CLOCK.NAME)
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@SIM.TICK=
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#ifdef @$(ACCESS)
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// Simulate the SDRAM
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// {{{
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(*m_@$(PREFIX))(m_core->o_@$(PREFIX)_cyc,
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m_core->o_@$(PREFIX)_stb,
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m_core->o_@$(PREFIX)_we,
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m_core->o_@$(PREFIX)_addr,
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&m_core->o_@$(PREFIX)_data,
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m_core->o_@$(PREFIX)_sel,
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m_core->i_@$(PREFIX)_stall,
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m_core->i_@$(PREFIX)_ack,
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&m_core->i_@$(PREFIX)_data);
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m_core->i_@$(PREFIX)_err = 0;
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// }}}
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#endif // @$(ACCESS)
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@SIM.LOAD=
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m_@$(PREFIX)->load(start, &buf[offset], wlen);
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