0923fdc0b6
add formal assertions using fifo to prove every wb request has a corresponding read/write command output
2023-06-15 17:43:15 +08:00
053a511144
set write-to-read delay for all banks for every write
2023-06-10 08:19:16 +08:00
806b49ebd5
changed folder name with underscore
2023-06-08 14:05:35 +08:00
f3e15e9ea4
added test 1: Sequential write then sequential read
2023-06-08 13:56:54 +08:00
2e6c2183aa
added sim duration for possible bus delays
2023-06-08 13:55:20 +08:00
de37c5a972
added wires for loadingg delay tap
2023-06-08 13:53:07 +08:00
b9204332b1
made delay tap loadable
2023-06-08 13:52:04 +08:00
c3707dab53
made delay tap loadable and made delay more flexible to use all 32 taps for both dqs and dq
2023-06-08 11:01:56 +08:00
98ed92a65b
added testbench for a single ddr3 device sim
2023-06-03 14:28:55 +08:00
9a19f82377
added testbench for model simulation
2023-06-03 14:24:11 +08:00
884fd2bcad
Add files via upload
2023-06-01 19:59:45 +08:00
6127bba77a
fixed data alignment for write operation, fixed CL and CWL for 100MHz:400MHz clk
2023-06-01 19:18:41 +08:00
26af4960e9
fixed display for prev_cmd and time difference
2023-06-01 19:15:36 +08:00
0a43b04f9e
added phy for generating differential o_ddr3_clk
2023-05-29 21:51:48 +08:00
d6b6c0b9a4
added o_ddr3_clk port
2023-05-29 21:48:44 +08:00
9e529131c0
fixed error "added_read_pipe has multiple drivers"
2023-05-29 20:52:48 +08:00
a56e6a8a24
changed write calibration pattern with high autocorrel stat
2023-05-29 16:40:41 +08:00
400a277cdc
added 52ns sync reset (IDELAYCTRL requirement)
2023-05-29 16:19:32 +08:00
02d512df55
Delete sdram.txt
2023-05-28 16:20:52 +08:00
12b533a9d1
added top module which instantiates the controller and phy
2023-05-28 16:20:22 +08:00
f648035e4e
added phy interface (separated from controller)
2023-05-28 16:19:47 +08:00
ab26902f7a
include only the controller (phy is now a separate module)
2023-05-28 16:18:14 +08:00
854839dde9
readme file from Micron
2023-05-28 16:14:21 +08:00
b9154a38bb
Delete rtl/DDR3 directory
...
clean-up the repo
2023-05-28 16:11:49 +08:00
fb8dd029e3
Delete ug586_7Series_MIS.pdf
2023-05-28 16:08:40 +08:00
6710b5b62b
Add files via upload
2023-05-25 19:14:12 +08:00
1e89a236df
fixed implementation errors in Vivado
2023-05-25 19:13:30 +08:00
a7de749ddf
Add files via upload
2023-05-22 19:53:20 +08:00
94d6253069
Add files via upload
2023-05-18 11:02:40 +08:00
991dcad40b
Add files via upload
2023-05-18 10:50:30 +08:00
8e6c422689
complete read and write calibration
2023-05-18 10:45:26 +08:00
c33bc40bd3
Update ddr3_controller.v
2023-05-11 15:35:34 +08:00
9be5b5a616
Update ddr3_controller.v
2023-05-11 14:49:47 +08:00
f3c4b1b465
Update ddr3_controller.v
2023-05-10 15:23:48 +08:00
c0172c24a3
added read phy interface
2023-04-27 19:40:35 +08:00
a5b14accf4
added PHY interface
2023-04-20 19:37:15 +08:00
060a0373e9
Update ddr3_controller.v
2023-04-06 19:56:55 +08:00
3b110018c7
Update ddr3_controller.v
2023-04-06 19:43:32 +08:00
fec8b5b3fc
Update ddr3_controller.v
2023-04-06 19:01:02 +08:00
ae201bfd04
removed irrelevant comments
2023-03-30 19:18:55 +08:00
192a9950e4
applied :retab
2023-03-30 18:27:58 +08:00
fa5fcc2615
use a 4-bit counter plus a 4-bit mask for tracking delay in every bank
...
this is the optimized delay-tracking mechanism on which the 32-bit shift regs is replaced by a 4-bit counter plus a 4-bit mask. This uses lower resources but still able to track the delays and the exact slot number where the delay is already satisfied (hence no added latency)
2023-03-30 18:17:46 +08:00
fa3f5e0d65
use 32-bit shift reg for tracking delay inside every bank
...
There are 4 delays being tracked (delay_before_precharge, delay_before_activate, delay_before_read, and delay_before_write) and 8 banks, that means 32x4x8 = 1024 bits needed for this tracking delay mechanism (totally wasteful!)
2023-03-30 18:14:09 +08:00
73e5f6b3de
added begin-end in short if-else statement
2023-03-23 20:35:37 +08:00
97092cf869
added logic for refresh sequence and bank access
2023-03-23 20:17:12 +08:00
adb21070d4
used :retab and fixed tab spacing
2023-03-09 18:14:58 +08:00
c5d387fa24
added reset sequence and formal assertions
...
- completed (mostly) the reset sequence
- added formal assertions and cover statements for reset sequence logic
- moved all parameters to this file
- fixed port widths
- converted IO ports to ANSI
2023-03-09 18:06:53 +08:00
71df6f7515
moved all parameters to the main verilog file
2023-03-09 18:01:58 +08:00
3633613c47
Update ddr3_controller.v
2023-03-02 20:12:28 +08:00
38109d8297
added initial RTLs
2023-03-02 20:04:37 +08:00
AngeloJacobo