added initial RTLs
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Angelo Jacobo
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// Background:
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// This DDR3 controller will be used with a DDR3-1600 with Kintex 7 FPGA Board (XC7K160T-3FFG676E).
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// The goal will be to:
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// - Run this at 1600Mbps (Maximum Physical Interface (PHY) Rate for a 4:1
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// memory controller based on "DC and AC Switching Characteristics" for Kintex 7)
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// - Parameterize everything
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// - Interface should be (nearly) bus agnostic
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// - High (sustained) data throughput. Sequential writes should be able to continue without interruption
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`default_nettype none
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`define DDR3_1600_11_11_11 // DDR3-1600 (11-11-11) speed bin
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`define RAM_1Gb //DDR3 Capacity
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//`define RAM_2Gb
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//`define RAM_4Gb
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//`define RAM_8Gb
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`define x8 //DDR3 organization (DQ bus width)
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//`define x4
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//`define x16
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module ddr3_controller #(
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parameter LANES = 8, //8 lanes of DQ
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parameter OPT_LOWPOWER = 1, //1 = low power, 0 = low logic
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parameter OPT_BUS_ABORT = 1 //1 = can abort bus, 0 = no abort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction)(
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)
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(
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i_clk, i_rst_n,
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// Wishbone inputs
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i_wb_cyc,
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i_wb_stb,
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i_wb_we,
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i_wb_addr,
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i_wb_data,
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i_wb_sel,
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i_aux,
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// Wishbone outputs
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o_wb_ack,
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o_wb_stall,
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o_wb_data,
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o_aux
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// PHY Interface (to be added later)
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////////////////////////////////////
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);
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`include "ddr3_parameters.vh"
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input wire i_clk, i_rst_n; //200MHz input clock
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// Wishbone inputs
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input wire i_wb_cyc; //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
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input wire i_wb_stb; //request a transfer
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input wire i_wb_we; //write-enable (1 = write, 0 = read)
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input wire[ADDR_BITS - 3 - 1:0] i_wb_addr; //{row, bank, col>>3}, this is WORD-ADRESSABLE (burst of 8 sequential address in 1 transaction)
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input wire[DQ_BITS*LANES*8 - 1:0] i_wb_data; //write data, 8 times the number of pins on the device (4:1 memory controller means 8 DDR transactions per controller clock)
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input wire[(DQ_BITS*LANES*8)/8 - 1:0] i_wb_sel; //byte strobe for write (1 = write the byte)
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input wire i_aux; //for AXI-interface compatibility (given upon strobe)
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// Wishbone outputs
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output reg o_wb_ack; //1 = read/write request has completed
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output reg o_wb_stall; //1 = busy, cannot accept requests
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output reg[DQ_BITS*LANES*8 - 1:0] o_wb_data; //read data, 8 times the number of pins on the device (4:1 memory controller means 8 DDR transactions per controller clock)
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output reg o_aux;//for AXI-interface compatibility (returned upon ack)
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//////////////////////////////////////////////////////// RESET and Initialization Procedure (JEDEC DDR3 doc pg. 19) ////////////////////////////////////////////////////////
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//This reset and initialization process is designed for simplicity. This uses a Read-Only Memory (ROM))
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//to store the {ddr3ddr3_commands,time_delay(19:0)}. The output is registered to
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reg[31:0] reset_initialization_rom[15:0];
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initial begin //{ { use-timer , stay-command , cke , reset_n } , CMD , TIMER or MRS}
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reset_initialization_rom[0] = {4'b1100 , CMD_NOP , ns_to_cycles(INITIAL_RESET_HIGH)};
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//1. RESET# needs to be maintained for minimum 200 us with stable power. CKE is pulled
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//“Low” anytime before RESET# being de-asserted (min. time 10 ns). .
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reset_initialization_rom[1] = {4'b1101 , CMD_NOP, ns_to_cycles(INITIAL_CKE_LOW)};
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//2. After RESET# is de-asserted, wait for another 500 us until CKE becomes active. During this time, the
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//DRAM will start internal state initialization; this will be done independently of external clocks.
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// .... Also, a NOP or Deselect command must be registered (with tIS set up time to clock) before
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//CKE goes active.
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reset_initialization_rom[2] = {4'b1111 , CMD_NOP, ns_to_cycles(TXPR)};
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//3. After CKE is being registered high, wait minimum of Reset CKE Exit time, tXPR.
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reset_initialization_rom[3] = {4'b0011, CMD_MRS, MR2[18:0]};
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//4. Delay of TMRD between MRS commands is 4nCK (DDR3 clock cycle). In a 4:1 controller, this is just a 1 clock cycle delay thus no delay is actually needed.
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end
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//notes:
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//ODT must be statically held low at all times (except for write of course) when RTT_NOM is enabled via MR1.
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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//convert nanoseconds time input to number of clock cycles (referenced to CONTROLLER_CLK_PERIOD)
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function [18:0] ns_to_cycles (input[19:0] ns);
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ns_to_cycles = $ceil(ns/CONTROLLER_CLK_PERIOD);
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endfunction
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`ifdef FORMAL
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end
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`endif
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endmodule
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@ -0,0 +1,176 @@
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// Some parameters are salvaged from Micron DDR3 Simulation Model Files ( https://www.micron.com/products/dram/ddr3-sdram/part-catalog/mt41k128m16jt-125 )
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localparam CONTROLLER_CLK_PERIOD = 5.0; //200MHz controller clock (5ns)
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localparam DDR3_CLK_PERIOD = 1.25; //800MHz DDR3 clock (1.25ns)
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////////////////////////////////////////////////////////////// COMMAND PARAMETERS //////////////////////////////////////////////////////////////
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//DDR3 commands {cs_n, ras_n, cas_n, we_n} (JEDEC DDR3 doc pg. 33 )
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localparam[3:0] CMD_MRS = 4'b0000; // Mode Register Set
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localparam[3:0] CMD_REF = 4'b0001; // Refresh
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localparam[3:0] CMD_PRE = 4'b0010; // Precharge (A10-AP: 0 = Single Bank Precharge, 1 = Precharge All Banks)
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localparam[3:0] CMD_ACT = 4'b0011; // Bank Activate
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localparam[3:0] CMD_WR = 4'b0100; // Write (A10-AP: 0 = no Auto-Precharge) (A12-BC#: 1 = Burst Length 8)
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localparam[3:0] CMD_RD = 4'b0101; //Read (A10-AP: 0 = no Auto-Precharge) (A12-BC#: 1 = Burst Length 8)
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localparam[3:0] CMD_NOP = 4'b0111; // No Operation
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localparam[3:0] CMD_DES = 4'b1000; // Deselect command performs the same function as No Operation command (JEDEC DDR3 doc pg. 34 NOTE 11)
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localparam[3:0] CMD_ZQC = 4'b0110; // ZQ Calibration (A10-AP: 0 = ZQ Calibration Short, 1 = ZQ Calibration Long)
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localparam RST_USE_TIMER = 26; // Command bit that determines if timer will be used
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localparam RST_STAY_COMMAND = 25; //Command bit that determines if command will last for entire timer duration (or if
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localparam RST_CKE = 24; //Control clock-enable input to DDR3
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localparam RST_RESET_N = 23; //Control reset to DDR3
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////// SET MODE REGISTERS //////////////////////////////////////////////////////////////
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localparam[2:0] PASR = 3'b000; //Partial Array Self-Refresh: Full Array
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localparam[2:0] CWL = 3'b011; //CAS write Latency: 8 (1.5 ns > tCK(avg) >= 1.25 ns)
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localparam ASR = 1'b1; //Auto Self-Refresh: on
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localparam SRT = 1'b0; //Self-Refresh Temperature Range:0 (If ASR = 1, SRT bit must be set to 0)
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localparam[1:0] RTT_WR = 2'b00; //Dynamic ODT: off
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localparam[18:0] MR2 = {3'b010, 5'b00000, RTT_WR, 1'b0, SRT, ASR, CWL, PASR};
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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localparam INITIAL_RESET_HIGH = 200_000; // 200us reset must be high at initialization
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localparam INITIAL_CKE_LOW = 500_000; // 500us cke must be low before activating
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`ifdef DDR3_1600_11_11_11 //DDR3-1600 (11-11-11) speed bin
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localparam TRAS = 35; // tRAS ns Minimum Active to Precharge command time
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localparam TRC = 48.750; // tRC ns Active to Active/Auto Refresh command time
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localparam TRCD = 13.750; // tRCD ns Active to Read/Write command time
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localparam TRP = 13.750; // tRP ns Precharge command period
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`endif
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`ifdef RAM_1Gb
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localparam TRFC = 110; // ns Refresh command to ACT or REF
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`elsif RAM_2Gb
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localparam TRFC = 160; // ns Refresh command to ACT or REF
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`elsif RAM_4Gb
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localparam TRFC = 300; // ns Refresh command to ACT or REF
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`else
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localparam TRFC = 350; // ns Refresh command to ACT or REF
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`endif
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localparam TXPR = max(5*DDR3_CLK_PERIOD,TRFC+10); // tXPR ns Exit Reset from CKE HIGH to a valid command
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localparam TMRD = 4; // tMRD nCK Mode Register Set command cycle time
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////// I/O Interface Width //////////////////////////////////////////////////////////////
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`ifdef RAM_1Gb
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`ifdef x4
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localparam DM_BITS = 1; // Set this localparam to control how many Data Mask bits are used
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localparam ADDR_BITS = 14 ; // MAX Address Bits
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localparam ROW_BITS = 14; // Set this localparam to control how many Address bits are used
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localparam COL_BITS = 11; // Set this localparam to control how many Column bits are used
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localparam DQ_BITS = 4 ; // Set this localparam to control how many Data bits are used **Same as part bit width**
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localparam DQS_BITS = 1 ; // Set this localparam to control how many Dqs bits are used
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`elsif x8
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localparam DM_BITS = 1; // Set this localparam to control how many Data Mask bits are used
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localparam ADDR_BITS = 14 ; // MAX Address Bits
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localparam ROW_BITS = 14; // Set this localparam to control how many Address bits are used
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localparam COL_BITS = 10; // Set this localparam to control how many Column bits are used
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localparam DQ_BITS = 8 ; // Set this localparam to control how many Data bits are used **Same as part bit width**
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localparam DQS_BITS = 1; // Set this localparam to control how many Dqs bits are used
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`else
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localparam DM_BITS = 2; // Set this localparam to control how many Data Mask bits are used
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localparam ADDR_BITS = 13 ; // MAX Address Bits
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localparam ROW_BITS = 13 ; // Set this localparam to control how many Address bits are used
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localparam COL_BITS = 10 ; // Set this localparam to control how many Column bits are used
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localparam DQ_BITS = 16; // Set this localparam to control how many Data bits are used **Same as part bit width**
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localparam DQS_BITS = 2; // Set this localparam to control how many Dqs bits are used
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`endif
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`elsif RAM_2Gb
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`ifdef x4
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localparam DM_BITS = 1 ; // Set this localparam to control how many Data Mask bits are used
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localparam ADDR_BITS = 15 ; // MAX Address Bits
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localparam ROW_BITS = 15; // Set this localparam to control how many Address bits are used
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localparam COL_BITS = 11; // Set this localparam to control how many Column bits are used
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localparam DQ_BITS = 4 ; // Set this localparam to control how many Data bits are used **Same as part bit width**
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localparam DQS_BITS = 1 ; // Set this localparam to control how many Dqs bits are used
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`elsif x8
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localparam DM_BITS = 1 // Set this localparam to control how many Data Mask bits are used
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localparam ADDR_BITS = 15 ; // MAX Address Bits
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localparam ROW_BITS = 15; // Set this localparam to control how many Address bits are used
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localparam COL_BITS = 10 ; // Set this localparam to control how many Column bits are used
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localparam DQ_BITS = 8; // Set this localparam to control how many Data bits are used **Same as part bit width**
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localparam DQS_BITS = 1 ; // Set this localparam to control how many Dqs bits are used
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`else
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localparam x16
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localparam DM_BITS = 2 ; // Set this localparam to control how many Data Mask bits are used
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localparam ADDR_BITS = 14 ; // MAX Address Bits
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localparam ROW_BITS = 14 ; // Set this localparam to control how many Address bits are used
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localparam COL_BITS = 10 ; // Set this localparam to control how many Column bits are used
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localparam DQ_BITS = 16 ; // Set this localparam to control how many Data bits are used **Same as part bit width**
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localparam DQS_BITS = 2 ; // Set this localparam to control how many Dqs bits are used
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`endif
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`elsif RAM_4Gb
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`ifdef x4
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localparam DM_BITS = 1; // Set this localparam to control how many Data Mask bits are used
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localparam ADDR_BITS = 16 ; // MAX Address Bits
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localparam ROW_BITS = 16; // Set this localparam to control how many Address bits are used
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localparam COL_BITS = 11; // Set this localparam to control how many Column bits are used
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localparam DQ_BITS = 4; // Set this localparam to control how many Data bits are used **Same as part bit width**
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localparam DQS_BITS = 1 ; // Set this localparam to control how many Dqs bits are used
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`elsif x8
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localparam DM_BITS = 1; // Set this localparam to control how many Data Mask bits are used
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localparam ADDR_BITS = 16 ; // MAX Address Bits
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localparam ROW_BITS = 16 ; // Set this localparam to control how many Address bits are used
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localparam COL_BITS = 10; // Set this localparam to control how many Column bits are used
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localparam DQ_BITS = 8 ; // Set this localparam to control how many Data bits are used **Same as part bit width**
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localparam DQS_BITS = 1 ; // Set this localparam to control how many Dqs bits are used
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`else
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localparam x16
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localparam DM_BITS = 2; // Set this localparam to control how many Data Mask bits are used
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localparam ADDR_BITS = 15 ; // MAX Address Bits
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localparam ROW_BITS = 15; // Set this localparam to control how many Address bits are used
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localparam COL_BITS = 10 ; // Set this localparam to control how many Column bits are used
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localparam DQ_BITS = 16; // Set this localparam to control how many Data bits are used **Same as part bit width**
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localparam DQS_BITS = 2 ; // Set this localparam to control how many Dqs bits are used
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`endif
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`else
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`ifdef x4
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localparam DM_BITS = 1 ; // Set this localparam to control how many Data Mask bits are used
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localparam ADDR_BITS = 16 ; // MAX Address Bits
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localparam ROW_BITS = 16; // Set this localparam to control how many Address bits are used
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localparam COL_BITS = 14; // Set this localparam to control how many Column bits are used
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localparam DQ_BITS = 4 ; // Set this localparam to control how many Data bits are used **Same as part bit width**
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localparam DQS_BITS = 1 ; // Set this localparam to control how many Dqs bits are used
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`elsif x8
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localparam DM_BITS = 1 ; // Set this localparam to control how many Data Mask bits are used
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localparam ADDR_BITS = 16 ; // MAX Address Bits
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localparam ROW_BITS = 16 ; // Set this localparam to control how many Address bits are used
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localparam COL_BITS = 11; // Set this localparam to control how many Column bits are used
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localparam DQ_BITS = 8 ; // Set this localparam to control how many Data bits are used **Same as part bit width**
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localparam DQS_BITS = 1 ; // Set this localparam to control how many Dqs bits are used
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`else
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localparam DM_BITS = 2; // Set this localparam to control how many Data Mask bits are used
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localparam ADDR_BITS = 16 ; // MAX Address Bits
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localparam ROW_BITS = 16; // Set this localparam to control how many Address bits are used
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localparam COL_BITS = 10; // Set this localparam to control how many Column bits are used
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localparam DQ_BITS = 16; // Set this localparam to control how many Data bits are used **Same as part bit width**
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localparam DQS_BITS = 2 ; // Set this localparam to control how many Dqs bits are used
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`endif
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`endif
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localparam BA_BITS = 3 ; // Set this parmaeter to control how many Bank Address bits are used
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localparam AP = 10 ; // the address bit that controls auto-precharge and precharge-all
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localparam BC = 12; // the address bit that controls burst chop
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function integer max(input integer a, input integer b);
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if(a >= b) max = a;
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else max = b;
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endfunction
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