James Cherry
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46c683814c
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sta130 write_verilog missing wire dcls for unconnected concatenation
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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2022-12-16 16:41:15 -10:00 |
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James Cherry
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3992c34aee
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OR-1465) write verilog module sort
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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2022-06-05 14:40:07 -07:00 |
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James Cherry
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2bc6e8f68c
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update copyright
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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2022-01-04 10:17:08 -07:00 |
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James Cherry
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65774f4bdd
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read_sdc gzip files
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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2021-11-14 17:53:25 -07:00 |
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James Cherry
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46a835a581
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write_verilog assigns for nets with multiple output ports
Signed-off-by: James Cherry <cherry@parallaxsw.com>
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2021-10-08 10:51:05 -07:00 |
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James Cherry
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2e8f0035dc
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update copyright
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2021-06-25 10:25:49 -07:00 |
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James Cherry
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61df23741d
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write_verilog w/o -include_pwr_gnd exclude top pwr/gnd port and dcl
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2021-02-19 09:06:27 -08:00 |
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James Cherry
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d00937f981
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write_verilog wire stmts
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2021-01-19 12:40:49 -07:00 |
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James Cherry
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78d29c8f90
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error/warn IDs
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2020-12-13 18:21:35 -07:00 |
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James Cherry
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01a1ab6707
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write_verilog -remove_cells
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2020-10-20 12:16:17 -07:00 |
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James Cherry
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fc279f0b34
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write_verilog -include_pwr_gnd
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2020-10-19 20:55:54 -07:00 |
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James Cherry
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a5722ae63c
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write_verilog remove_cells use std::vector
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2020-07-15 11:56:11 -07:00 |
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James Cherry
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4fa9e46235
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write_verilog -remove_cells
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2020-07-15 07:56:34 -07:00 |
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James Cherry
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e7ed3170f3
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write_verilog power/ground port dcls
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2020-07-03 16:56:15 -07:00 |
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James Cherry
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ec856896c7
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verilog read/write to public includes
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2020-04-05 16:56:38 -07:00 |
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James Cherry
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ee326f165c
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public headers in include/sta
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2020-04-05 14:53:44 -07:00 |
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James Cherry
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804953e317
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mv public headers to include/sta
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2020-04-05 11:35:51 -07:00 |
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James Cherry
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4a017e86eb
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update copyright
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2020-03-06 18:50:37 -08:00 |
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James Cherry
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74e287a7eb
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write_verilog escaped bus port name "input [7:0] \in[0] ;"
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2019-07-03 21:18:38 -07:00 |
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James Cherry
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7af69066df
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VerilogWriter use liberty bus port order
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2019-07-02 16:33:31 -07:00 |
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James Cherry
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eb9fdd1be0
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write verilog match liberty bus bit order
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2019-07-02 07:07:34 -07:00 |
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James Cherry
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d108a15c56
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write_verilog fails for missing pins
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2019-06-27 18:04:57 -07:00 |
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James Cherry
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5d7ad0a1ef
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write_verilog use concat for instance bus ports
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2019-06-27 16:06:46 -07:00 |
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James Cherry
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1a84830895
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sta::worst_slack args, sta to verilog name args
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2019-06-18 15:52:12 -07:00 |
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James Cherry
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eea6ab1a29
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write_verilog -sorted -> -sort
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2019-06-17 12:33:37 -07:00 |
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James Cherry
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3f7e207491
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write_verilog
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2019-06-16 21:08:00 -07:00 |