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golden
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Update golden results for FreePDK45 tests.
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2018-07-27 14:25:52 -07:00 |
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00_code_format_check_test.py
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resolved variable name error in 00_code_format test
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2018-08-15 03:33:33 -07:00 |
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01_library_drc_test.py
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Remove extra conversion to list
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2018-07-11 12:07:37 -07:00 |
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02_library_lvs_test.py
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Fix option reload problems and checkpointing so that it works properly.
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2018-07-11 12:00:15 -07:00 |
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03_contact_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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03_path_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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03_ptx_1finger_nmos_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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03_ptx_1finger_pmos_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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03_ptx_3finger_nmos_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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03_ptx_3finger_pmos_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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03_ptx_4finger_nmos_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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03_ptx_4finger_pmos_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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03_wire_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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04_pbitcell_test.py
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Remove carriage returns form python files
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2018-08-07 09:44:01 -07:00 |
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04_pinv_1x_beta_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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04_pinv_1x_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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04_pinv_2x_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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04_pinv_10x_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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04_pinvbuf_test.py
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Fix pinvbuf test to use new interface with only driver size.
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2018-07-26 14:20:00 -07:00 |
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04_pnand2_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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04_pnand3_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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04_pnor2_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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04_precharge_test.py
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Merging changes to bank. Bank has been altered to accommodate multiport. Single port still passes unit test, though some control signal names have been changed to have a following 0 (e.g. s_en to s_en0). Multiport does not pass drc yet, but can accurately generate a spice netlist.
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2018-08-15 04:00:48 -07:00 |
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04_single_level_column_mux_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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05_bitcell_array_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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05_pbitcell_array_test.py
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Add +x permissions on precharge and pbitcell tests
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2018-08-13 09:57:10 -07:00 |
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06_hierarchical_decoder_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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06_hierarchical_predecode2x4_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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06_hierarchical_predecode3x8_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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07_single_level_column_mux_array_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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08_precharge_array_test.py
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Altered bank to accommodate multiport. Single port still works, though some of the control signal names have been changes to have a following 0 (e.g. s_en to s_en0). Multiport does not pass drc yet, but can generate an accurate spice netlist.
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2018-08-15 03:36:40 -07:00 |
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08_wordline_driver_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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09_sense_amp_array_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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10_write_driver_array_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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11_dff_array_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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11_dff_buf_array_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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11_dff_buf_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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11_dff_inv_array_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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11_dff_inv_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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11_ms_flop_array_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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12_tri_gate_array_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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13_delay_chain_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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14_replica_bitline_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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16_control_logic_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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19_bank_select_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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19_multi_bank_test.py
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Clean up tests. Enable 8-way tests. Some tests still have channel route conflicts.
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2018-07-17 15:13:00 -07:00 |
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19_single_bank_test.py
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Clean up tests. Enable 8-way tests. Some tests still have channel route conflicts.
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2018-07-17 15:13:00 -07:00 |
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20_sram_1bank_test.py
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Connect data and column DFF clocks in 1 bank.
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2018-08-14 10:09:41 -07:00 |
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20_sram_2bank_test.py
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Fix syntax error in unit test
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2018-07-17 15:14:22 -07:00 |
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20_sram_4bank_test.py
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Clean up tests. Enable 8-way tests. Some tests still have channel route conflicts.
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2018-07-17 15:13:00 -07:00 |
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21_hspice_delay_test.py
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Update delay results with new clock routing
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2018-08-14 10:51:02 -07:00 |
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21_hspice_setuphold_test.py
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Update format of delay test output during an error to directly
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2018-07-26 16:05:24 -07:00 |
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21_ngspice_delay_test.py
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Update delay results with new clock routing
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2018-08-14 10:51:02 -07:00 |
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21_ngspice_setuphold_test.py
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Update format of delay test output during an error to directly
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2018-07-26 16:05:24 -07:00 |
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22_pex_test.py
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Fix option reload problems and checkpointing so that it works properly.
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2018-07-11 12:00:15 -07:00 |
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22_sram_func_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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23_lib_sram_model_test.py
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Updated output messages in timing test comparisons.
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2018-07-27 09:34:44 -07:00 |
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23_lib_sram_prune_test.py
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Updated output messages in timing test comparisons.
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2018-07-27 09:34:44 -07:00 |
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23_lib_sram_test.py
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Update remaining SCMOS golden lib files.
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2018-07-27 09:44:12 -07:00 |
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24_lef_sram_test.py
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Disable LEF test until supplies fixed.
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2018-07-11 14:18:53 -07:00 |
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25_verilog_sram_test.py
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Modify unit tests to reset options during init_openram so
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2018-07-10 16:39:32 -07:00 |
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30_openram_test.py
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Close output log in test 30 to avoid warning
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2018-07-26 14:01:40 -07:00 |
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config_20_freepdk45.py
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Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken.
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2018-02-12 09:33:23 -08:00 |
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config_20_scn3me_subm.py
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Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken.
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2018-02-12 09:33:23 -08:00 |
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regress.py
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Add DRC/LVS/PEX statistics in verbose=1 mode
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2018-07-11 11:59:24 -07:00 |
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testutils.py
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Update golden results for FreePDK45 tests.
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2018-07-27 14:25:52 -07:00 |
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