OpenRAM/compiler/modules
Eren Dogan f8b2c1e9b9 Change OPTS.route_supplies option since there's only one router now 2023-08-02 21:48:29 -07:00
..
__init__.py
and2_dec.py
and3_dec.py
and4_dec.py
bank.py
bitcell_1port.py
bitcell_2port.py
bitcell_array.py
bitcell_base.py
bitcell_base_array.py
capped_replica_bitcell_array.py
col_cap_array.py
col_cap_bitcell_1port.py
col_cap_bitcell_2port.py
column_decoder.py
column_mux.py
column_mux_array.py
control_logic.py
control_logic_base.py
control_logic_delay.py
delay_chain.py
dff.py
dff_array.py
dff_buf.py
dff_buf_array.py
dff_inv.py
dff_inv_array.py
dummy_array.py
dummy_bitcell_1port.py
dummy_bitcell_2port.py
dummy_pbitcell.py
global_bitcell_array.py
hierarchical_decoder.py
hierarchical_predecode.py
hierarchical_predecode2x4.py
hierarchical_predecode3x8.py
hierarchical_predecode4x16.py
internal_base.py
inv_dec.py
local_bitcell_array.py
multi_delay_chain.py
multibank.py
nand2_dec.py
nand3_dec.py
nand4_dec.py
orig_bitcell_array.py
pand2.py
pand3.py
pand4.py
pbitcell.py
pbuf.py
pbuf_dec.py
pdriver.py
pgate.py
pinv.py
pinv_dec.py
pinvbuf.py
pnand2.py
pnand3.py
pnand4.py
pnor2.py
port_address.py
port_data.py
precharge.py
precharge_array.py
ptristate_inv.py
ptx.py
pwrite_driver.py
replica_bitcell_1port.py
replica_bitcell_2port.py
replica_bitcell_array.py
replica_column.py
replica_pbitcell.py
rom_address_control_array.py
rom_address_control_buf.py
rom_bank.py
rom_base_array.py
rom_base_cell.py
rom_column_mux.py
rom_column_mux_array.py
rom_control_logic.py
rom_decoder.py
rom_poly_tap.py
rom_precharge_array.py
rom_precharge_cell.py
rom_wordline_driver_array.py
row_cap_array.py
row_cap_bitcell_1port.py
row_cap_bitcell_2port.py
sense_amp.py
sense_amp_array.py
sram_1bank.py
sram_multibank.py
sram_multibank_template.v
template.py
tri_gate.py
tri_gate_array.py
wordline_buffer_array.py
wordline_driver.py
wordline_driver_array.py
write_driver.py
write_driver_array.py
write_mask_and_array.py