mrg c1fedda575 Modifications for min area metal. ... Made add_via_stack_center iterative instead of recursive. Removed add_via_stack (non-center) since it isn't used. Add min area metal during iterative via insertion.		2020-06-30 15:07:34 -07:00
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base	Modifications for min area metal.	2020-06-30 15:07:34 -07:00
bitcells	Error out on single port in sky130	2020-06-22 15:41:59 -07:00
characterizer	DRC/LVS and errors fixes.	2020-06-30 07:16:05 -07:00
custom	Change s8 to sky130	2020-06-12 14:23:26 -07:00
datasheet	Convert capital names to lower case for consistency	2019-08-21 13:45:34 -07:00
drc	PEP8 cleanup	2020-04-15 11:24:28 -07:00
example_configs	revert example scn4m to non netlist only	2020-02-09 23:52:11 -08:00
gdsMill	added purposes to addText(), removed reference to specific tech from gdsMill	2020-02-19 16:26:52 -08:00
modules	Don't route to clk to perimeter on m2	2020-06-30 13:57:45 -07:00
pgates	Modifications for min area metal.	2020-06-30 15:07:34 -07:00
router	Changes to simplify metal preferred directions and pitches.	2020-05-10 11:32:45 -07:00
sram	Extra track in data bus. Remove old code.	2020-06-30 10:58:24 -07:00
tests	Skip test in sky130	2020-06-29 15:28:16 -07:00
verify	DRC/LVS and errors fixes.	2020-06-30 07:16:05 -07:00
Makefile	Clean up Makefile for unit tests	2018-12-05 12:58:10 -08:00
debug.py	DRC/LVS and errors fixes.	2020-06-30 07:16:05 -07:00
gen_stimulus.py	Fixed errors in extra rows characterization	2020-03-22 20:54:49 +00:00
globals.py	Change s8 to sky130	2020-06-12 14:23:26 -07:00
openram.py	Characterization for extra rows	2020-02-20 17:01:52 +00:00
options.py	move accuracy_requirement from techfile to config	2020-06-25 06:44:07 -07:00
run_profile.sh	Convert pin map to a set for faster membership.	2019-04-01 15:45:44 -07:00
sram_factory.py	Auto-generate port dependent cell names.	2020-06-05 15:09:22 -07:00
view_profile.py	Remove some flake8 errors/warnings.	2019-10-02 23:26:02 +00:00