| .. |
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golden
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Reapply jsowash update without spice model file
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2019-06-24 08:59:58 -07:00 |
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00_code_format_check_test.py
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Merge branch 'pep8_cleanup' into dev
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2019-06-14 08:47:10 -07:00 |
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01_library_drc_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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02_library_lvs_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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03_contact_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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03_path_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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03_ptx_1finger_nmos_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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03_ptx_1finger_pmos_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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03_ptx_3finger_nmos_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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03_ptx_3finger_pmos_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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03_ptx_4finger_nmos_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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03_ptx_4finger_pmos_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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03_wire_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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04_dummy_pbitcell_test.py
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Replica bitcell array with arbitrary RBLs working
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2019-07-10 15:56:51 -07:00 |
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04_pand2_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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04_pbitcell_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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04_pbuf_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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04_pdriver_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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04_pinv_1x_beta_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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04_pinv_1x_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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04_pinv_2x_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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04_pinv_10x_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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04_pinvbuf_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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04_pnand2_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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04_pnand3_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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04_pnor2_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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04_precharge_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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04_replica_pbitcell_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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04_single_level_column_mux_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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05_bitcell_1rw_1r_array_test.py
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Clean up multiport test options to be consistent.
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2019-07-12 10:39:55 -07:00 |
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05_bitcell_array_test.py
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Merge branch 'dev' into rbl_revamp
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2019-07-03 14:05:28 -07:00 |
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05_dummy_array_test.py
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Re-enable replica tests
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2019-07-03 14:57:47 -07:00 |
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05_pbitcell_array_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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05_replica_pbitcell_array_test.py
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Add pbitcell RW test
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2019-07-16 11:54:39 -07:00 |
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06_hierarchical_decoder_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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06_hierarchical_predecode2x4_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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06_hierarchical_predecode3x8_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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07_single_level_column_mux_array_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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08_precharge_array_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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08_wordline_driver_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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09_sense_amp_array_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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10_write_driver_array_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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11_dff_array_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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11_dff_buf_array_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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11_dff_buf_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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12_tri_gate_array_test.py
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Merge branch 'dev' into rbl_revamp
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2019-07-03 14:05:28 -07:00 |
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13_delay_chain_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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14_replica_bitcell_1rw_1r_array_test.py
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Remove old replica bitline.
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2019-07-18 15:19:40 -07:00 |
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14_replica_bitcell_array_test.py
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Remove old replica bitline.
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2019-07-18 15:19:40 -07:00 |
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14_replica_column_test.py
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Remove old replica bitline.
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2019-07-18 15:19:40 -07:00 |
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16_control_logic_multiport_test.py
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Removed write_size from parameters.
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2019-07-21 15:53:05 -07:00 |
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16_control_logic_test.py
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Fix bitline names in merge error
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2019-07-26 22:03:50 -07:00 |
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18_port_address_test.py
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Create port address module
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2019-07-05 09:03:52 -07:00 |
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18_port_data_test.py
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Single banks working with new RBL
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2019-07-11 14:47:27 -07:00 |
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19_bank_select_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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19_multi_bank_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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19_pmulti_bank_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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19_psingle_bank_test.py
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Cleanup unit test. Fix s_en control bug for r-only.
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2019-07-16 13:51:31 -07:00 |
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19_single_bank_1rw_1r_test.py
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Clean up multiport test options to be consistent.
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2019-07-12 10:39:55 -07:00 |
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19_single_bank_1w_1r_test.py
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Cleanup unit test. Fix s_en control bug for r-only.
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2019-07-16 13:51:31 -07:00 |
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19_single_bank_test.py
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Single banks working with new RBL
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2019-07-11 14:47:27 -07:00 |
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20_psram_1bank_2mux_1rw_1w_test.py
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Clean up multiport test options to be consistent.
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2019-07-12 10:39:55 -07:00 |
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20_psram_1bank_2mux_1w_1r_test.py
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Clean up multiport test options to be consistent.
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2019-07-12 10:39:55 -07:00 |
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20_psram_1bank_2mux_test.py
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Clean up multiport test options to be consistent.
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2019-07-12 10:39:55 -07:00 |
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20_psram_1bank_4mux_1rw_1r_test.py
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Clean up multiport test options to be consistent.
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2019-07-12 10:39:55 -07:00 |
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20_sram_1bank_2mux_1rw_1r_test.py
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Clean up multiport test options to be consistent.
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2019-07-12 10:39:55 -07:00 |
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20_sram_1bank_2mux_1w_1r_test.py
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Clean up multiport test options to be consistent.
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2019-07-12 10:39:55 -07:00 |
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20_sram_1bank_2mux_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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20_sram_1bank_4mux_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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20_sram_1bank_8mux_1rw_1r_test.py
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Clean up multiport test options to be consistent.
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2019-07-12 10:39:55 -07:00 |
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20_sram_1bank_8mux_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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20_sram_1bank_nomux_1rw_1r_test.py
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Clean up multiport test options to be consistent.
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2019-07-12 10:39:55 -07:00 |
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20_sram_1bank_nomux_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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20_sram_2bank_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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21_hspice_delay_test.py
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Update spice results
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2019-07-27 12:13:44 -07:00 |
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21_hspice_setuphold_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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21_model_delay_test.py
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Minor cleanup. Skip more tests until analytical fixed.
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2019-07-26 08:33:06 -07:00 |
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21_ngspice_delay_test.py
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Update spice results
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2019-07-27 12:13:44 -07:00 |
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21_ngspice_setuphold_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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22_psram_1bank_2mux_func_test.py
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Fix bad indent.
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2019-07-27 11:14:56 -07:00 |
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22_psram_1bank_4mux_func_test.py
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Fix ALL of the indents.
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2019-07-27 11:30:48 -07:00 |
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22_psram_1bank_8mux_func_test.py
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Fix ALL of the indents.
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2019-07-27 11:30:48 -07:00 |
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22_psram_1bank_nomux_func_test.py
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Fixed control problems (probably)
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2019-07-27 11:09:08 -07:00 |
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22_psram_wmask_func_test.py
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Add dummy pbitcell
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2019-07-27 12:13:35 -07:00 |
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22_sram_1bank_2mux_func_test.py
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Fixed control problems (probably)
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2019-07-27 11:09:08 -07:00 |
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22_sram_1bank_4mux_func_test.py
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Fixed control problems (probably)
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2019-07-27 11:09:08 -07:00 |
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22_sram_1bank_8mux_func_test.py
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Fixed control problems (probably)
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2019-07-27 11:09:08 -07:00 |
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22_sram_1bank_nomux_func_test.py
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Fixed control problems (probably)
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2019-07-27 11:09:08 -07:00 |
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22_sram_1rw_1r_1bank_nomux_func_test.py
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Fix ALL of the indents.
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2019-07-27 11:30:48 -07:00 |
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22_sram_wmask_func_test.py
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Fix ALL of the indents.
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2019-07-27 11:30:48 -07:00 |
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23_lib_sram_model_corners_test.py
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Skip model tests for now
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2019-07-25 14:46:33 -07:00 |
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23_lib_sram_model_test.py
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Skip model tests for now
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2019-07-25 14:46:33 -07:00 |
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23_lib_sram_prune_test.py
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Skip prune test for now
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2019-07-25 14:49:11 -07:00 |
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23_lib_sram_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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24_lef_sram_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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25_verilog_sram_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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26_hspice_pex_pinv_test.py
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fix the delay measure bug in pex tests
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2019-07-10 04:39:40 -07:00 |
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26_ngspice_pex_pinv_test.py
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fix the delay measure bug in pex tests
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2019-07-10 04:39:40 -07:00 |
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26_pex_test.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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30_openram_back_end_test.py
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Minor cleanup. Skip more tests until analytical fixed.
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2019-07-26 08:33:06 -07:00 |
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30_openram_front_end_test.py
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Minor cleanup. Skip more tests until analytical fixed.
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2019-07-26 08:33:06 -07:00 |
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config_freepdk45.py
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Fix space before comment
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2019-06-14 08:43:41 -07:00 |
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config_freepdk45_back_end.py
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Use non-analytical models for now
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2019-07-25 14:55:42 -07:00 |
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config_freepdk45_front_end.py
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Use non-analytical models for now
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2019-07-25 14:55:42 -07:00 |
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config_scn3me_subm.py
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Remove useless comments. Add missing copyright.
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2019-06-14 10:13:13 -07:00 |
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config_scn3me_subm_back_end.py
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Use non-analytical models for now
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2019-07-25 14:55:42 -07:00 |
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config_scn3me_subm_front_end.py
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Use non-analytical models for now
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2019-07-25 14:55:42 -07:00 |
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config_scn4m_subm.py
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Fix space before comment
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2019-06-14 08:43:41 -07:00 |
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config_scn4m_subm_back_end.py
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Use non-analytical models for now
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2019-07-25 14:55:42 -07:00 |
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config_scn4m_subm_front_end.py
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Minor cleanup. Skip more tests until analytical fixed.
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2019-07-26 08:33:06 -07:00 |
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regress.py
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Merge branch 'pep8_cleanup' into dev
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2019-06-14 08:47:10 -07:00 |
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sram_1rw_1r_tb.v
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Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.
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2019-01-11 14:15:16 -08:00 |
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sram_1rw_tb.v
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Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.
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2019-01-11 14:15:16 -08:00 |
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sram_1rw_wmask_tb.v
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Verified 1rw mask writing and changed verilog.py accordingly.
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2019-07-05 15:08:59 -07:00 |
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testutils.py
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Merge remote-tracking branch 'origin/dev' into rbl_revamp
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2019-07-12 11:10:07 -07:00 |
8e43469486