Matt Guthaus 583dc4410b Revert bus bits back into pins

2019-02-22 16:22:27 -08:00

..

golden

Revert bus bits back into pins

2019-02-22 16:22:27 -08:00

00_code_format_check_test.py

Check for print statements in more files since we now use print_raw

2019-01-18 10:16:55 -08:00

01_library_drc_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

02_library_lvs_test.py

Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.

2018-11-07 11:31:44 -08:00

03_contact_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

03_path_test.py

Change path to wire_path for Anaconda package conflict

2019-01-25 15:07:56 -08:00

03_ptx_1finger_nmos_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

03_ptx_1finger_pmos_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

03_ptx_3finger_nmos_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

03_ptx_3finger_pmos_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

03_ptx_4finger_nmos_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

03_ptx_4finger_pmos_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

03_wire_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

04_pand2_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

04_pbitcell_test.py

Add the factory class

2019-01-16 17:04:28 -08:00

04_pbuf_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

04_pdriver_test.py

Change pbuf/pinv to pdriver in control logic.

2019-01-23 12:03:52 -08:00

04_pinv_1x_beta_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

04_pinv_1x_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

04_pinv_2x_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

04_pinv_10x_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

04_pinvbuf_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

04_pnand2_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

04_pnand3_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

04_pnor2_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

04_precharge_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

04_replica_pbitcell_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

04_single_level_column_mux_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

05_bitcell_1rw_1r_array_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

05_bitcell_array_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

05_pbitcell_array_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

06_hierarchical_decoder_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

06_hierarchical_predecode2x4_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

06_hierarchical_predecode3x8_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

07_single_level_column_mux_array_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

08_precharge_array_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

08_wordline_driver_test.py

Convert wordline driver to use sized pdriver

2019-01-24 10:20:23 -08:00

09_sense_amp_array_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

10_write_driver_array_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

11_dff_array_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

11_dff_buf_array_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

11_dff_buf_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

12_tri_gate_array_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

13_delay_chain_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

14_replica_bitline_multiport_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

14_replica_bitline_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

16_control_logic_test.py

Fixed bug in control logic test with port configs.

2019-02-06 20:09:01 -08:00

19_bank_select_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

19_multi_bank_test.py

Output number of words per row before SRAM creation. Recompute words per row in unit tests.

2018-12-06 13:11:47 -08:00

19_pmulti_bank_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

19_psingle_bank_test.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

19_single_bank_1rw_1r_test.py

Add multiport bank test

2018-11-13 16:06:21 -08:00

19_single_bank_test.py

Clean up psingle_bank_test

2018-11-09 09:34:34 -08:00

20_psram_1bank_2mux_1rw_1w_test.py

Output number of words per row before SRAM creation. Recompute words per row in unit tests.

2018-12-06 13:11:47 -08:00

20_psram_1bank_2mux_1w_1r_test.py

Output number of words per row before SRAM creation. Recompute words per row in unit tests.

2018-12-06 13:11:47 -08:00

20_psram_1bank_2mux_test.py

Output number of words per row before SRAM creation. Recompute words per row in unit tests.

2018-12-06 13:11:47 -08:00

20_psram_1bank_4mux_1rw_1r_test.py

Output number of words per row before SRAM creation. Recompute words per row in unit tests.

2018-12-06 13:11:47 -08:00

20_sram_1bank_2mux_1rw_1r_test.py

Output number of words per row before SRAM creation. Recompute words per row in unit tests.

2018-12-06 13:11:47 -08:00

20_sram_1bank_2mux_test.py

Output number of words per row before SRAM creation. Recompute words per row in unit tests.

2018-12-06 13:11:47 -08:00

20_sram_1bank_4mux_test.py

Output number of words per row before SRAM creation. Recompute words per row in unit tests.

2018-12-06 13:11:47 -08:00

20_sram_1bank_8mux_1rw_1r_test.py

Output number of words per row before SRAM creation. Recompute words per row in unit tests.

2018-12-06 13:11:47 -08:00

20_sram_1bank_8mux_test.py

Output number of words per row before SRAM creation. Recompute words per row in unit tests.

2018-12-06 13:11:47 -08:00

20_sram_1bank_nomux_1rw_1r_test.py

Output number of words per row before SRAM creation. Recompute words per row in unit tests.

2018-12-06 13:11:47 -08:00

20_sram_1bank_nomux_test.py

Output number of words per row before SRAM creation. Recompute words per row in unit tests.

2018-12-06 13:11:47 -08:00

20_sram_2bank_test.py

Output number of words per row before SRAM creation. Recompute words per row in unit tests.

2018-12-06 13:11:47 -08:00

21_hspice_delay_test.py

Changed test values to fix tests.

2019-02-06 15:27:29 -08:00

21_hspice_setuphold_test.py

Moved feasible period search from functional.py to tests.

2018-12-05 23:23:40 -08:00

21_ngspice_delay_test.py

Adjusted test values to account for recent changes.

2019-02-05 00:43:16 -08:00

21_ngspice_setuphold_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

22_psram_1bank_2mux_func_test.py

Merged with dev, removed commented out code.

2018-12-12 16:02:16 -08:00

22_psram_1bank_4mux_func_test.py

Merged with dev, removed commented out code.

2018-12-12 16:02:16 -08:00

22_psram_1bank_8mux_func_test.py

Merged with dev, removed commented out code.

2018-12-12 16:02:16 -08:00

22_psram_1bank_nomux_func_test.py

Merged with dev, removed commented out code.

2018-12-12 16:02:16 -08:00

22_sram_1bank_2mux_func_test.py

Merged with dev, removed commented out code.

2018-12-12 16:02:16 -08:00

22_sram_1bank_4mux_func_test.py

Merged with dev, removed commented out code.

2018-12-12 16:02:16 -08:00

22_sram_1bank_8mux_func_test.py

Merged with dev, removed commented out code.

2018-12-12 16:02:16 -08:00

22_sram_1bank_nomux_func_test.py

Output number of words per row before SRAM creation. Recompute words per row in unit tests.

2018-12-06 13:11:47 -08:00

22_sram_1rw_1r_1bank_nomux_func_test.py

Merged with dev, removed commented out code.

2018-12-12 16:02:16 -08:00

23_lib_sram_model_test.py

Output number of words per row before SRAM creation. Recompute words per row in unit tests.

2018-12-06 13:11:47 -08:00

23_lib_sram_prune_test.py

Output number of words per row before SRAM creation. Recompute words per row in unit tests.

2018-12-06 13:11:47 -08:00

23_lib_sram_test.py

Output number of words per row before SRAM creation. Recompute words per row in unit tests.

2018-12-06 13:11:47 -08:00

24_lef_sram_test.py

Add assert to lef and verilog unit test. Fix verilog files in golden results.

2019-01-11 16:42:50 -08:00

25_verilog_sram_test.py

Add assert to lef and verilog unit test. Fix verilog files in golden results.

2019-01-11 16:42:50 -08:00

26_pex_test.py

Fix error in 8mux test. Fix comment in all tests.

2018-11-02 16:34:26 -07:00

27_worst_case_delay_test.py

Output number of words per row before SRAM creation. Recompute words per row in unit tests.

2018-12-06 13:11:47 -08:00

28_delay_model_test.py

Added data collection of wordline and s_en measurements.

2019-01-17 01:59:41 -08:00

30_openram_test.py

Check for coverage executable and run without if not found.

2019-01-09 08:24:20 -08:00

config_20_freepdk45.py

Rewrote pin enclosure code to better address off grid pins.

2018-10-10 15:15:58 -07:00

config_20_scn3me_subm.py

Rewrote pin enclosure code to better address off grid pins.

2018-10-10 15:15:58 -07:00

config_20_scn4m_subm.py

Rewrote pin enclosure code to better address off grid pins.

2018-10-10 15:15:58 -07:00

config_data.py

Added more variance analysis for the delay data

2019-02-07 02:27:22 -08:00

delay_data_collection.py

Made variance plot look slightly better.

2019-02-07 15:30:47 -08:00

regress.py

Add DRC/LVS/PEX statistics in verbose=1 mode

2018-07-11 11:59:24 -07:00

sram_1rw_1r_tb.v

Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.

2019-01-11 14:15:16 -08:00

sram_1rw_tb.v

Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.

2019-01-11 14:15:16 -08:00

testutils.py

Merge branch 'dev' into multiport_characterization

2019-02-07 14:31:26 -08:00