mirror of https://github.com/VLSIDA/OpenRAM.git
113 lines
4.1 KiB
Python
113 lines
4.1 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import bitcell_base_array
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from globals import OPTS
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from sram_factory import factory
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from vector import vector
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import debug
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class local_bitcell_array(bitcell_base_array.bitcell_base_array):
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"""
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A local bitcell array is a bitcell array with a wordline driver.
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This can either be a single aray on its own if there is no hierarchical WL
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or it can be combined into a larger array with hierarchical WL.
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"""
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def __init__(self, rows, cols, ports, left_rbl=0, right_rbl=0, add_replica=True, name=""):
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super().__init__(name, rows, cols, 0)
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debug.info(2, "create local array of size {} rows x {} cols words".format(rows,
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cols + left_rbl + right_rbl))
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self.rows = rows
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self.cols = cols
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self.left_rbl = left_rbl
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self.right_rbl = right_rbl
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self.all_ports = ports
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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# We don't offset this because we need to align
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# the replica bitcell in the control logic
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# self.offset_all_coordinates()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place()
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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# This is just used for names
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self.cell = factory.create(module_type="bitcell")
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self.bitcell_array = factory.create(module_type="replica_bitcell_array",
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cols=self.cols,
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rows=self.rows,
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left_rbl=self.left_rbl,
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right_rbl=self.right_rbl,
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bitcell_ports=self.all_ports)
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self.add_mod(self.bitcell_array)
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self.wl_array = factory.create(module_type="wordline_buffer_array",
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rows=self.rows + len(self.all_ports),
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cols=self.cols)
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self.add_mod(self.wl_array)
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def add_pins(self):
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self.bitline_names = self.bitcell_array.get_all_bitline_names()
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self.add_pin_list(self.bitline_names, "INOUT")
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self.wordline_names = self.bitcell_array.get_all_wordline_names()
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self.add_pin_list(self.wordline_names, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_instances(self):
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""" Create the module instances used in this design """
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internal_wl_names = [x + "i" for x in self.wordline_names]
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self.wl_inst = self.add_inst(name="wl_driver",
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mod=self.wl_array)
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self.connect_inst(self.wordline_names + internal_wl_names + ["vdd", "gnd"])
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self.array_inst = self.add_inst(name="array",
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mod=self.bitcell_array,
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offset=self.wl_inst.lr())
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self.connect_inst(self.bitline_names + internal_wl_names + ["vdd", "gnd"])
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def place(self):
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""" Place the bitcelll array to the right of the wl driver. """
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self.wl_inst.place(vector(0, 0))
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self.array_inst.place(self.wl_inst.lr())
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self.height = self.bitcell_array.height
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self.width = self.array_inst.rx()
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def add_layout_pins(self):
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for (x, y) in zip(self.bitline_names, self.bitcell_array.get_inouts()):
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self.copy_layout_pin(self.array_inst, y, x)
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for (x, y) in zip(self.wordline_names, self.wl_array.get_inputs()):
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self.copy_layout_pin(self.wl_inst, y, x)
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