mrg 8f2d787d53 Add min area metal in preferred direction

2022-05-11 10:50:32 -07:00

..

channel_route.py

Remove breakpoint

2022-03-07 16:59:55 -08:00

contact.py

Update copyright year.

2021-01-22 11:23:28 -08:00

custom_cell_properties.py

Rework replica_bitcell_array supplies

2022-04-19 08:50:11 -07:00

custom_layer_properties.py

fix freepdk45

2021-06-17 03:21:01 -07:00

delay_data.py

Update copyright year.

2021-01-22 11:23:28 -08:00

design.py

Move power supply stack to design

2022-02-18 15:02:45 -08:00

errors.py

Add exception errors file

2020-04-08 16:55:45 -07:00

geometry.py

Merge remote-tracking branch 'bvhoof/dev' into dev

2021-03-01 12:16:26 -08:00

hierarchy_design.py

By default uniquify instances based on macro name.

2022-03-11 18:01:45 -08:00

hierarchy_layout.py

Add min area metal in preferred direction

2022-05-11 10:50:32 -07:00

hierarchy_spice.py

Add per tool lvs directories

2021-12-17 10:21:34 -08:00

lef.py

Improve supply routing for ring and side pins

2021-05-28 10:58:30 -07:00

pin_layout.py

Fix width of replica routes. Don't enclose pins if they overlap sufficiently.

2022-05-09 11:44:46 -07:00

power_data.py

Update copyright year.

2021-01-22 11:23:28 -08:00

route.py

Update copyright year.

2021-01-22 11:23:28 -08:00

timing_graph.py

Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage.

2021-09-07 15:56:27 -07:00

utils.py

fix bias correspondence points

2021-06-30 05:21:39 -07:00

vector.py

PEP8 cleanup

2021-09-07 16:49:44 -07:00

verilog.py

Move mem reg before usage for compatibility

2021-10-13 09:46:02 -07:00

wire_path.py

Update copyright year.

2021-01-22 11:23:28 -08:00

wire_spice_model.py

Added unit r and c values with m2 minwidth incorporated to match CACTI params

2021-08-01 00:23:59 -07:00

wire.py

Update copyright year.

2021-01-22 11:23:28 -08:00