mrg 2011974e01 Make drc and lvs errors a member variable. Run only once.		2020-07-13 12:49:24 -07:00
..
base	Make drc and lvs errors a member variable. Run only once.	2020-07-13 12:49:24 -07:00
bitcells	Error out on single port in sky130	2020-06-22 15:41:59 -07:00
characterizer	Make drc and lvs errors a member variable. Run only once.	2020-07-13 12:49:24 -07:00
custom	Change s8 to sky130	2020-06-12 14:23:26 -07:00
datasheet	…
drc	PEP8 cleanup	2020-04-15 11:24:28 -07:00
example_configs	Make drc and lvs errors a member variable. Run only once.	2020-07-13 12:49:24 -07:00
gdsMill	added purposes to addText(), removed reference to specific tech from gdsMill	2020-02-19 16:26:52 -08:00
modules	Simplify write mask supply via logic	2020-07-01 14:44:48 -07:00
pgates	Modifications for min area metal.	2020-06-30 15:07:34 -07:00
router	Changes to simplify metal preferred directions and pitches.	2020-05-10 11:32:45 -07:00
sram	Make drc and lvs errors a member variable. Run only once.	2020-07-13 12:49:24 -07:00
tests	Fail unit test, but mention if LVS passes and DRC fails.	2020-06-30 16:22:44 -07:00
verify	Move magic/netgen files to tech dir	2020-07-09 11:33:14 -07:00
Makefile	…
debug.py	DRC/LVS and errors fixes.	2020-06-30 07:16:05 -07:00
gen_stimulus.py	Fixed errors in extra rows characterization	2020-03-22 20:54:49 +00:00
globals.py	Change s8 to sky130	2020-06-12 14:23:26 -07:00
openram.py	Add words_per_row and others in config file.	2020-07-13 12:37:56 -07:00
options.py	Add words_per_row and others in config file.	2020-07-13 12:37:56 -07:00
run_profile.sh	…
sram_factory.py	Auto-generate port dependent cell names.	2020-06-05 15:09:22 -07:00
view_profile.py	Remove some flake8 errors/warnings.	2019-10-02 23:26:02 +00:00