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OpenRAM/compiler/tests
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Michael Timothy Grimes 4d3f01ff2f The bitcell currently passes DRC and LVS for FreePDK45 and SCMOS 
There are 2 benchtests for the bitcell:
1) one with 2 write ports and 2 read ports
2) one with 2 write ports and 0 read ports
The second test is meant to show how the bitcell functions when read/write ports are
used instead of separate ports for read and write
The bitcell currently passes both tests in both technologies
Certain sizing optimizations still need to be done on the bitcell
 		2018-02-28 11:14:53 -08:00
..
golden Fixed leakage and power unit test results. 2018-02-23 15:20:52 -08:00
#03_ptx_4finger_pmos_test.py# Fail simulation tests if correct spice is not found. Correctly load spice characterizer. 2018-01-26 13:00:25 -08:00
00_code_format_check_test.py Add utility script gen_stimulus.py to help create simulations for debugging. 2018-02-26 08:54:35 -08:00
01_library_drc_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
02_library_lvs_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
03_contact_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
03_path_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
03_ptx_1finger_nmos_test.py Only perform DRC not LVS on transistors 2018-01-30 08:03:54 -08:00
03_ptx_1finger_pmos_test.py Only perform DRC not LVS on transistors 2018-01-30 08:03:54 -08:00
03_ptx_3finger_nmos_test.py Only perform DRC not LVS on transistors 2018-01-30 08:03:54 -08:00
03_ptx_3finger_pmos_test.py Only perform DRC not LVS on transistors 2018-01-30 08:03:54 -08:00
03_ptx_4finger_nmos_test.py Only perform DRC not LVS on transistors 2018-01-30 08:03:54 -08:00
03_ptx_4finger_pmos_test.py Only perform DRC not LVS on transistors 2018-01-30 08:03:54 -08:00
03_wire_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
04_pbitcell_0R_test.py The bitcell currently passes DRC and LVS for FreePDK45 and SCMOS 2018-02-28 11:14:53 -08:00
04_pbitcell_test.py The bitcell currently passes DRC and LVS for FreePDK45 and SCMOS 2018-02-28 11:14:53 -08:00
04_pinv_1x_beta_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
04_pinv_1x_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
04_pinv_2x_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
04_pinv_10x_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
04_pnand2_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
04_pnand3_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
04_pnor2_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
04_precharge_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
04_wordline_driver_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
05_bitcell_array_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
06_hierarchical_decoder_test.py Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder. 2018-02-02 14:08:56 -08:00
06_hierarchical_predecode2x4_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
06_hierarchical_predecode3x8_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
07_single_level_column_mux_array_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
08_precharge_array_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
09_sense_amp_array_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
10_write_driver_array_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
11_dff_array_test.py Connect dff array clk in rows and columns. 2018-02-14 16:46:26 -08:00
11_ms_flop_array_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
12_tri_gate_array_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
13_delay_chain_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
14_replica_bitline_test.py Fix unit test to have fanout. 2018-02-16 11:53:38 -08:00
16_control_logic_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
19_multi_bank_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
19_single_bank_test.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
20_sram_1bank_test.py Disable virtual connects at top level LVS with Calibre. 2018-02-05 14:52:51 -08:00
20_sram_2bank_test.py Disable virtual connects at top level LVS with Calibre. 2018-02-05 14:52:51 -08:00
20_sram_4bank_test.py Disable virtual connects at top level LVS with Calibre. 2018-02-05 14:52:51 -08:00
21_hspice_delay_test.py Fixed leakage and power unit test results. 2018-02-23 15:20:52 -08:00
21_hspice_setuphold_test.py Update golden lib tests. Add new generic SCMOS models. Fix tech error with new msflop_in_cap name. 2018-02-13 15:54:50 -08:00
21_ngspice_delay_test.py Fixed leakage and power unit test results. 2018-02-23 15:20:52 -08:00
21_ngspice_setuphold_test.py Fix unit tests with newest RBL delays. Fix tech problem with new spice models. 2018-02-16 13:54:05 -08:00
22_pex_func_test_with_pinv.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
22_sram_func_test.py Fix syntax error in functional test. 2018-02-23 07:47:01 -08:00
23_lib_sram_model_test.py Add new corner-based lib files to unit tests. 2018-02-11 16:35:10 -08:00
23_lib_sram_prune_test.py Add new corner-based lib files to unit tests. 2018-02-11 16:35:10 -08:00
23_lib_sram_test.py Add new corner-based lib files to unit tests. 2018-02-11 16:35:10 -08:00
24_lef_sram_test.py Modify unit tests to distinguish between FAIL and ERROR. Move comparison utilities into our derived unit test class. 2018-01-31 11:48:41 -08:00
25_verilog_sram_test.py Modify unit tests to distinguish between FAIL and ERROR. Move comparison utilities into our derived unit test class. 2018-01-31 11:48:41 -08:00
30_openram_test.py Fix three unit tests to work with new lib corner files. 2018-02-11 20:43:41 -08:00
README RELEASE 1.0 2016-11-08 09:57:35 -08:00
config_20_freepdk45.py Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken. 2018-02-12 09:33:23 -08:00
config_20_scn3me_subm.py Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken. 2018-02-12 09:33:23 -08:00
regress.py Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
testutils.py Disable virtual connects at top level LVS with Calibre. 2018-02-05 14:52:51 -08:00

README 

Note that the tests turn off DRC/LVS when they perform their own check
for performance improvement. However, it must be turned back on before
the test runs an assert.