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bank.py
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Use lower case names except for leaf cells and top level
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2018-07-18 15:10:57 -07:00 |
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bank_select.py
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Consolidate metal pitch rules to new design class
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2018-07-09 15:42:46 -07:00 |
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bitcell.py
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changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit
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2018-05-22 14:16:51 -07:00 |
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bitcell_array.py
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simplfying calculations in pbitcell and changing pbitcell_array_test to check different port combinations
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2018-05-31 17:39:51 -07:00 |
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control_logic.py
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Convert bank to use create_bus routines.
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2018-07-16 14:13:41 -07:00 |
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delay_chain.py
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Add internal vdd/gnd connections for delay chain
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2018-07-19 10:37:47 -07:00 |
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dff.py
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Add dff_buf for buffered flop arrays.
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2018-03-04 16:13:10 -08:00 |
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dff_array.py
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Fix routing clk connections of dff arrays
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2018-07-18 11:38:58 -07:00 |
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dff_buf.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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dff_buf_array.py
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Fix routing clk connections of dff arrays
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2018-07-18 11:38:58 -07:00 |
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dff_inv.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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dff_inv_array.py
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Fix routing clk connections of dff arrays
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2018-07-18 11:38:58 -07:00 |
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hierarchical_decoder.py
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Use lower case names except for leaf cells and top level
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2018-07-18 15:10:57 -07:00 |
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hierarchical_predecode.py
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Fix spacing between adjacent decoders
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2018-07-17 15:01:16 -07:00 |
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hierarchical_predecode2x4.py
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First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
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2018-02-26 16:32:28 -08:00 |
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hierarchical_predecode3x8.py
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First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
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2018-02-26 16:32:28 -08:00 |
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ms_flop.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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ms_flop_array.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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precharge_array.py
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Route precharge_array vdd in M3
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2018-04-04 13:49:55 -07:00 |
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replica_bitcell.py
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Organize top-level files into subdirs.
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2018-02-09 10:25:24 -08:00 |
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replica_bitline.py
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Add new supplies to RBL and control logic
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2018-07-16 12:58:15 -07:00 |
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sense_amp.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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sense_amp_array.py
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Fix sense amp spacing after modifying index to be increment by one.
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2018-06-29 15:30:17 -07:00 |
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single_level_column_mux_array.py
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Consolidate metal pitch rules to new design class
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2018-07-09 15:42:46 -07:00 |
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tri_gate.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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tri_gate_array.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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wordline_driver.py
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Move supply to M3 in wordline driver
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2018-04-11 16:23:45 -07:00 |
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write_driver.py
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Organize top-level files into subdirs.
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2018-02-09 10:25:24 -08:00 |
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write_driver_array.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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