OpenRAM/compiler
jcirimel 02e65a00ef update pex to work with dev changes 2020-08-03 17:14:34 -07:00
..
base fix merge conflicts 2020-07-21 11:38:34 -07:00
bitcells update to new metal stack names 2020-07-31 05:27:19 -07:00
characterizer update pex to work with dev changes 2020-08-03 17:14:34 -07:00
custom Change s8 to sky130 2020-06-12 14:23:26 -07:00
datasheet Convert capital names to lower case for consistency 2019-08-21 13:45:34 -07:00
drc PEP8 cleanup 2020-04-15 11:24:28 -07:00
example_configs fix merge conflicts 2020-07-21 11:38:34 -07:00
gdsMill added purposes to addText(), removed reference to specific tech from gdsMill 2020-02-19 16:26:52 -08:00
modules fix merge conflicts 2020-07-21 11:38:34 -07:00
pgates Clean up binning. Fix mults to 1 for certain gates. 2020-07-15 17:15:42 -07:00
router Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
sram update pex to work with dev changes 2020-08-03 17:14:34 -07:00
tests Fail unit test, but mention if LVS passes and DRC fails. 2020-06-30 16:22:44 -07:00
verify update pex to work with dev changes 2020-08-03 17:14:34 -07:00
Makefile Clean up Makefile for unit tests 2018-12-05 12:58:10 -08:00
debug.py DRC/LVS and errors fixes. 2020-06-30 07:16:05 -07:00
gen_stimulus.py Fixed errors in extra rows characterization 2020-03-22 20:54:49 +00:00
globals.py Change s8 to sky130 2020-06-12 14:23:26 -07:00
openram.py Add words_per_row and others in config file. 2020-07-13 12:37:56 -07:00
options.py Add words_per_row and others in config file. 2020-07-13 12:37:56 -07:00
run_profile.sh Convert pin map to a set for faster membership. 2019-04-01 15:45:44 -07:00
sram_factory.py Auto-generate port dependent cell names. 2020-06-05 15:09:22 -07:00
view_profile.py Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00