15 Commits

Author	SHA1	Message	Date
Hunter Nichols	1236a0773a	Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage.	2021-09-07 15:56:27 -07:00
Hunter Nichols	6b8d143073	Changed cacti RC delay function to better match cacti code in bitcell. Sense amp also has similar changed but is missing transconductance parameter.	2021-09-01 14:27:13 -07:00
Hunter Nichols	680d7b5d93	Added special RC delay functions for the bitline and sense amp to match CACTI. Contains temporary parameters which need to be defined.	2021-08-25 16:12:05 -07:00
Hunter Nichols	b3500982ca	Fixed issue with wire resistance in total resistance equations for cacti. Fixed issue with sense amp resistance values.	2021-08-04 16:10:27 -07:00
Hunter Nichols	10085d85ab	Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files.	2021-07-21 14:59:02 -07:00
Hunter Nichols	1acc10e9d5	Added name changes to on resistance params. Added input capacitance functions to relevant modules for CACTI input load functions.	2021-07-21 12:24:08 -07:00
Hunter Nichols	2c9f755a73	Added on resistance functions for pgates, custom cells, and bitcell.	2021-07-12 14:25:37 -07:00
Matt Guthaus	30fc81a1f0	Update copyright year.	2021-01-22 11:23:28 -08:00
Hunter Nichols	7a0f5e15db	Added polarity checks in modules to allow to make it easier to get spice rise/fall. Path measures not failing now but should be changed later.	2020-11-17 15:05:07 -08:00
mrg	902b92223f	Small fix for finding pin names in timing graph.	2020-11-16 13:57:31 -08:00
mrg	1d729e8f02	Move pin name mapping to layout class.	2020-11-16 11:04:03 -08:00
mrg	e4bc2c4914	Update property settings with getters/setters	2020-11-14 08:08:42 -08:00
mrg	b4342ac527	More cleanup	2020-11-13 17:29:20 -08:00
mrg	8021430122	Fix pbitcell erros	2020-11-13 15:55:55 -08:00
mrg	1890385be1	Use custom cells when needed.	2020-11-03 11:58:25 -08:00