luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,617 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

4617 Commits

Author SHA1 Message Date
Matt Guthaus ffcf58100e Clean up column mux by moving pins to own function. Adjust spacing between column mux and bitcell to prevent DRCs. Fix up find lowest/highest functions when no objects or instances in a module. 2018-02-02 15:17:21 -08:00
Matt Guthaus 9d043b904e Remove unnecessary design reset 2018-02-02 14:26:53 -08:00
Matt Guthaus 27dbb95c19 Fix name of column mux. 2018-02-02 14:26:39 -08:00
Matt Guthaus 9d7dc4c552 Reset even if not purging temp files. 2018-02-02 14:26:09 -08:00
Matt Guthaus 2a8199c3ca Force re-extract of cells in DRC/LVS. 2018-02-02 14:21:31 -08:00
Matt Guthaus fb90b8f5fe Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder. 2018-02-02 14:08:56 -08:00
Matt Guthaus 3be59fb762 Change DRC output for magic to drc.summary just like calibre output. 2018-02-02 14:07:15 -08:00
Hunter Nichols 3d4e4c9ceb Fixed merge conflicts with remote 2018-02-02 13:08:59 -08:00
Matt Guthaus 63392c8d71 Fix gnd connection in control logic. 2018-02-02 13:04:38 -08:00
Matt Guthaus 072c8e3174 Change LVS report file to same name as Calibre 2018-02-02 12:47:42 -08:00
Hunter Nichols db4913dd9c Added skeleton code for analytical power in functions with analytical delay. 2018-02-02 12:31:34 -08:00
Matt Guthaus 74064fc854 Replace LEF files with new changes. 2018-02-02 12:31:34 -08:00
Matt Guthaus e8d001a3f9 Change wen to en in spice lib files. Check lvs report insted of stdout with netgen. 2018-02-02 12:31:33 -08:00
Matt Guthaus e4295ea61b Fix pin names to lower case. Fix write driver DRC errors and LVS error. 2018-02-02 12:31:33 -08:00
Matt Guthaus 3e2d4d631d Do not require hspice during tests. Check if a valid simulator is found, however. 2018-02-02 12:31:33 -08:00
Matt Guthaus 7c9c16e29c Fix assertion error syntax problem. Do not require hspice for functional test. Improve delay fail error message. 2018-02-02 12:31:33 -08:00
Matt Guthaus cc987daeb9 Add well around column muxes. 2018-02-02 12:31:33 -08:00
mguthaus 2ad52205c5 Clean up messages. 2018-02-02 12:31:33 -08:00
mguthaus d0c9382d97 Modify unit tests to distinguish between FAIL and ERROR. Move comparison utilities into our derived unit test class. 2018-02-02 12:31:33 -08:00
Hunter Nichols 56f7caf59f Added first test power model to sram 2018-02-02 12:31:33 -08:00
Matt Guthaus 5527e73db0 Add descriptive exceptions along with cleanup in unit test checking. 2018-02-02 12:31:33 -08:00
Matt Guthaus e983047402 Fix via1 BL disconnect error. 2018-02-02 12:31:33 -08:00
Matt Guthaus be1c59f10c Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array. 2018-02-02 12:31:33 -08:00
Matt Guthaus ea5eda91fc Connect all gnd rails of RBL. 2018-02-02 12:27:24 -08:00
Matt Guthaus d552d88f45 Add -d option to not delete temp directory on successful runs. 2018-02-01 11:53:02 -08:00
Matt Guthaus 8ef1e0af2c Replace LEF files with new changes. 2018-02-01 05:43:37 -08:00
Matt Guthaus 64546ad3dd Change wen to en in spice lib files. Check lvs report insted of stdout with netgen. 2018-02-01 05:38:48 -08:00
Matt Guthaus 512448f9e8 Fix pin names to lower case. Fix write driver DRC errors and LVS error. 2018-01-31 17:37:16 -08:00
Matt Guthaus 9fea4a1a2d Do not require hspice during tests. Check if a valid simulator is found, however. 2018-01-31 16:21:43 -08:00
Matt Guthaus 590f6e01d1 Fix assertion error syntax problem. Do not require hspice for functional test. Improve delay fail error message. 2018-01-31 15:38:02 -08:00
Matt Guthaus acf3fe8376 Add well around column muxes. 2018-01-31 14:31:50 -08:00
mguthaus 4273a3717d Clean up messages. 2018-01-31 11:54:20 -08:00
mguthaus 4aee700331 Modify unit tests to distinguish between FAIL and ERROR. Move comparison utilities into our derived unit test class. 2018-01-31 11:48:41 -08:00
Hunter Nichols 621de4b47b Added first test power model to sram 2018-01-31 11:45:12 -08:00
Matt Guthaus 1175f515c8 Add descriptive exceptions along with cleanup in unit test checking. 2018-01-31 10:35:51 -08:00
Matt Guthaus 51a72e26c7 Fix via1 BL disconnect error. 2018-01-31 10:35:28 -08:00
Matt Guthaus 58da8af619 Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array. 2018-01-31 10:04:28 -08:00
Matt Guthaus 012c3923be Create empty setup.tcl file as workaround for resetting netgen LVS options until Tim fix's bug. 2018-01-31 08:28:53 -08:00
Matt Guthaus 9d10ccff37 Remove spice model dir env variable for scn3me. 2018-01-30 10:54:29 -08:00
Matt Guthaus 264d55b16c Remove temp files 2018-01-30 08:05:50 -08:00
Matt Guthaus 8fcb551953 Only perform DRC not LVS on transistors 2018-01-30 08:03:54 -08:00
Matt Guthaus 1d9274621a Only remove files when cleaning temp dir 2018-01-30 07:58:31 -08:00
Matt Guthaus c63eb3be3b Fixed bug with missing tri gate via. 2018-01-29 17:29:30 -08:00
Matt Guthaus 0b6eddef43 Force write the specific cell during DRC. 2018-01-29 17:00:20 -08:00
Matt Guthaus 56770f558f Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
Matt Guthaus 313e06d2af Fix pwell contact in column mux to have layers for Magic. 2018-01-29 15:53:22 -08:00
Matt Guthaus 6080b59058 Fix nand input ordering to correct netgen LVS error of wordline driver. 2018-01-29 15:36:37 -08:00
Matt Guthaus a56fa0e787 Fix wrong pin order on pnand2 LVS problem. 2018-01-29 15:31:14 -08:00
Matt Guthaus 8fcc8a1674 Increase height slightlty to allow pnand3 to pass DRC. 2018-01-29 15:30:58 -08:00
Matt Guthaus 79715ae1a2 Fix input discrepencies in pre3x8 2018-01-29 15:25:41 -08:00