luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Added first test power model to sram

This commit is contained in:
Hunter Nichols 2018-01-31 11:45:12 -08:00
parent 1175f515c8
commit 621de4b47b
2 changed files with 10 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
compiler/characterizer/delay.py
View File

@ -451,15 +451,17 @@ class delay():
LH_slew.append(bank_delay.slew/1e3)
HL_slew.append(bank_delay.slew/1e3)
power = sram.analytical_power(slew, load)
data = {"min_period": 0,
"delay1": LH_delay,
"delay0": HL_delay,
"slew1": LH_slew,
"slew0": HL_slew,
"read0_power": 0,
"read1_power": 0,
"write0_power": 0,
"write1_power": 0
"read0_power": power,
"read1_power": power,
"write0_power": power,
"write1_power": power
}
return data

4
compiler/sram.py
View File

@ -1003,3 +1003,7 @@ class sram(design.design):
def analytical_delay(self,slew,load):
""" LH and HL are the same in analytical model. """
return self.bank.analytical_delay(slew,load)
def analytical_power(self,slew,load):
""" Just a test function for the power."""
return 1