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OpenRAM
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1543 Commits

Author SHA1 Message Date
Matt Guthaus 831e454b34 Remove redundant DRC run in magic. 2018-11-05 13:30:42 -08:00
Matt Guthaus f3d1f7d55b Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2018-11-05 13:15:25 -08:00
Matt Guthaus cf4c138032 Small updates to CONTRIBUTING.md 2018-11-05 13:14:16 -08:00
Matt Guthaus 37b81c0af1 Remove options from example config files 2018-11-05 12:47:47 -08:00
Matt Guthaus 02bafb4757 Merge remote-tracking branch 'origin/dev' into supply_routing 2018-11-05 12:44:46 -08:00
Matt Guthaus 67dbb4893e Merge remote-tracking branch 'origin/dev' into multiport 2018-11-05 12:43:32 -08:00
Matt Guthaus 0ec16c2b68 Modify replica cell spice in FreePDK45 to short Qbar to vdd 2018-11-05 11:42:42 -08:00
Matt Guthaus de6d9d4699 Change freepdk45 rbl cell too. 2018-11-05 11:02:11 -08:00
Matt Guthaus 3c5dc70ede Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd. 2018-11-05 10:59:08 -08:00
Hunter Nichols 9744bc516a Merge branch 'dev' into multiport_characterization 2018-11-05 10:40:29 -08:00
Matt Guthaus ce94366a1d Skip all 4mux and 8mux tests until we solve teh simulation timing bug. 2018-11-05 09:50:44 -08:00
Michael Timothy Grimes 3c9821991b Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-11-05 08:56:19 -08:00
Matt Guthaus 38dab77bfc Add fixed seed to functional test during unit tests. Skip non-working tests after fixed seed. 2018-11-03 10:53:09 -07:00
Matt Guthaus 5d2df76ef5 Skip 4mux test 2018-11-03 10:16:22 -07:00
Matt Guthaus 5ecfa88d2a Pad the routing grid by a few tracks to add an extra rail 2018-11-02 17:35:35 -07:00
Matt Guthaus a3666d82ab Reduce verbosity of level 1 debug. 2018-11-02 17:30:28 -07:00
Hunter Nichols 7461f2b1bf Merged with dev. 2018-11-02 17:22:09 -07:00
Hunter Nichols f05865b307 Fixed drc issues with replica bitline test. 2018-11-02 17:16:41 -07:00
Matt Guthaus f8e761313a Merge branch 'dev' into supply_routing 2018-11-02 16:39:49 -07:00
Matt Guthaus 852bfbc031 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2018-11-02 16:34:36 -07:00
Matt Guthaus 6dd959b638 Fix error in 8mux test. Fix comment in all tests. 2018-11-02 16:34:26 -07:00
Matt Guthaus ad1d3a3c78 Use default grid costs again. 2018-11-02 16:04:56 -07:00
Matt Guthaus 3950a9feff Merge branch 'supply_routing' into dev 2018-11-02 15:31:29 -07:00
Matt Guthaus 74c3de2812 Remove diagonal routing bug. Cleanup. 2018-11-02 14:57:40 -07:00
Matt Guthaus 6d48bdf55a Merge branch 'supply_routing' into dev 2018-11-02 11:51:32 -07:00
Matt Guthaus 33bbe3fd68 Merge branch 'supply_routing' of github.com:VLSIDA/PrivateRAM into supply_routing 2018-11-02 11:51:11 -07:00
Matt Guthaus ac203d987c Merge branch 'supply_routing' into dev 2018-11-02 11:50:46 -07:00
Matt Guthaus 866eaa8b02 Add debug message when routes are diagonal. 2018-11-02 11:50:28 -07:00
Matt Guthaus 7e39150c38 Merge branch 'supply_routing' of https://github.com/VLSIDA/PrivateRAM into supply_routing 2018-11-02 11:13:34 -07:00
Matt Guthaus 56fa274a5e Merge branch 'supply_routing' of https://github.com/VLSIDA/PrivateRAM into supply_routing 2018-11-02 11:12:35 -07:00
Matt Guthaus 4d30f214da Add expanded blockages for paths an enclosures to handle wide metal spacing rules. 2018-11-02 11:11:32 -07:00
Matt Guthaus 4e09f0a944 Change layer text to comment to avoid glade reserved keyword 2018-11-02 10:58:00 -07:00
Michael Timothy Grimes 6711630463 Altering the routing slightly in the column mux to give the gnd contacts a wider berth. This prevents drc errors when the bitlines are close to the edge of the cell. 2018-11-02 05:59:47 -07:00
Hunter Nichols 642dc8517c Added no mux functional test for 1rw+1r. Delay characterization also works for the custom cell as well. 2018-11-01 14:05:55 -07:00
Jesse Cirimelli-Low 3fa1d5522e added DRC/LVS error count to datasheet 2018-11-01 14:02:33 -07:00
Hunter Nichols b00fc040a3 Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos. 2018-11-01 12:29:49 -07:00
Matt Guthaus b24c8a42a1 Remove redundant pins in pin_group constructor. Clean up some code and comments. 2018-11-01 11:31:24 -07:00
Michael Timothy Grimes dc96d86082 Optimizations to pbitcell spacings 2018-11-01 07:58:20 -07:00
Matt Guthaus 2eedc703d1 Rename function in pin_group 2018-10-31 16:13:28 -07:00
Matt Guthaus c511d886bf Added new enclosure connector algorithm using edge sorting. 2018-10-31 15:35:39 -07:00
Jesse Cirimelli-Low ce5001e0af added config file to datasheet and output files 2018-10-31 12:29:13 -07:00
Jesse Cirimelli-Low c3d7e24df9 fixed broken links when -o flag set 2018-10-31 09:34:36 -07:00
Matt Guthaus 673027ac8c Moved assert to check out_path earlier. 
Preserve temporary output directory with -d option.
 2018-10-31 09:37:47 -07:00
Hunter Nichols 9321f0461b Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r. 2018-10-31 00:06:34 -07:00
Jesse Cirimelli-Low 5302fd205f fixed some final typos in datasheet 2018-10-30 23:03:05 -07:00
Jesse Cirimelli-Low 70ac2e8aa4 changed css to orange and black for Halloween; fixed CSb timing table in datasheet 2018-10-30 22:56:13 -07:00
Jesse Cirimelli-Low fe196c23a9 added FF timing information 2018-10-30 22:32:19 -07:00
Hunter Nichols e5dcf5d5b1 Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass. 2018-10-30 22:19:26 -07:00
Jesse Cirimelli-Low 905f6f8b43 added docstring and renamed some functions 2018-10-30 21:37:30 -07:00
Matt Guthaus fc45242ccb Allow contains to contain copy. Add connectors when pin doesn't overlap grids. 2018-10-30 17:41:29 -07:00