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OpenRAM
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77 Commits

Author SHA1 Message Date
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
Hunter Nichols d08181455c Added multiport bitcell support for storage node checks 2019-05-20 22:50:03 -07:00
Hunter Nichols 099bc4e258 Added bitcell check to storage nodes. 2019-05-20 18:35:52 -07:00
Hunter Nichols d8617acff2 Merged with dev 2019-05-15 18:48:00 -07:00
Hunter Nichols 178d3df5f5 Added graph to characterizer to get net names and perform s_en checks. Graph not working with column mux. 2019-05-14 14:44:49 -07:00
Hunter Nichols d54074d68e Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based. 2019-05-07 00:52:27 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 05ad4285af Cleanup pgate code. 
Moved create_netlist and create_layout to the pgate class
from which everything is derived. Modified all pgates
to have consistent debug output and order of init function.
 2019-04-26 12:30:42 -07:00
Hunter Nichols c1411f4227 Applied quick corner estimation to analytical delay. 2019-04-09 12:26:54 -07:00
Hunter Nichols 80a325fe32 Added corner information for analytical power estimation. 2019-03-04 19:27:53 -08:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Matt Guthaus 091b4e4c62 Add size commments to spize. Change pdriver stage effort. 2019-01-23 17:27:15 -08:00
Matt Guthaus a418431a42 First draft of sram_factory code 2019-01-16 16:15:38 -08:00
Matt Guthaus 5de7ff3773 Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench. 2019-01-11 14:15:16 -08:00
Matt Guthaus e2cfd382b9 Fix print check regression 2018-10-15 13:23:31 -07:00
Matt Guthaus 6220ea6d47 Update router to work with pin_layout structure. 2018-08-29 15:34:45 -07:00
Matt Guthaus 138a70fc23 Add place_inst routine. 
Separate create netlist and layout in some modules.
 2018-08-27 10:42:40 -07:00
Matt Guthaus f34c4eb7dc Convert entire OpenRAM to use python3. Works with Python 3.6. 
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
 2018-05-14 16:15:45 -07:00
Matt Guthaus bab92fcf38 Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works. 2018-03-23 08:13:20 -07:00
Matt Guthaus b867e163a6 Move label pins to center like layout pins. 
Rework of control logic with vertical poly. Passes DRC/LVS.
Single bank passing DRC.
 2018-03-23 08:12:59 -07:00
Matt Guthaus 7293eb33bc Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev 2018-03-02 10:30:16 -08:00
Matt Guthaus 2b839d34a3 Get rid of netgen error of undefined dlatch. Fix sp_read to find correct subckt name and pins. 2018-02-27 08:59:46 -08:00
Hunter Nichols 62ad30e741 Added initial version of analytical power esitmation. Loops through instances but power estimate is not accurate. 2018-02-22 19:35:54 -08:00
Hunter Nichols beb7dad9bc Added corner paramters to power functions. This commit does not compile (sorry) 2018-02-22 00:15:55 -08:00
Hunter Nichols d4a0f48d4f Added power calculations for inverter. Still testing. 2018-02-21 19:51:21 -08:00
Matt Guthaus 7100d6f904 Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00