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OpenRAM
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26 Commits

Author SHA1 Message Date
mrg d8baa5384d Remove useless comments. Add missing copyright. 2019-06-14 10:13:13 -07:00
Matt Guthaus 6e044b776f Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
mrg d789f93743 Add debug runner during individual tests. 2019-05-31 10:51:42 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 0354e2dfb7 Rename config_20 to config since it is used in all tests 2019-03-08 10:47:41 -08:00
Matt Guthaus 09a429aef7 Update unit tests to all use the sram_factory 2019-03-06 14:12:24 -08:00
Matt Guthaus a418431a42 First draft of sram_factory code 2019-01-16 16:15:38 -08:00
Hunter Nichols 8257e4fe8c Changed syntax in replica_bl tests, golden data to fit new values in delay tests. 2018-11-19 16:51:43 -08:00
Matt Guthaus 6ac5adaeca Separate multiport replica bitline from regular replica bitline test 2018-11-14 11:41:09 -08:00
Hunter Nichols 7461f2b1bf Merged with dev. 2018-11-02 17:22:09 -07:00
Matt Guthaus 6dd959b638 Fix error in 8mux test. Fix comment in all tests. 2018-11-02 16:34:26 -07:00
Hunter Nichols b00fc040a3 Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos. 2018-11-01 12:29:49 -07:00
Matt Guthaus 6bbf66d55b Rewrote pin enclosure code to better address off grid pins. 
Include only maximal pin enclosure shapes.
Add smallest area connector for off grid pins.
Fix decoder to use add_power_pin code.
Change permissions.
 2018-10-10 15:15:58 -07:00
Michael Timothy Grimes f1560375fc Altering control logic for read ports and write ports, by including only read or write specific circuitry. Altering replica bitline layout to support multiport 2018-09-25 20:00:25 -07:00
Michael Timothy Grimes e0b9989d85 Adding replica_pbitcell and test for multi-ported purposes. Altering replica bitline and test to accomodate. 2018-09-13 01:42:06 -07:00
Matt Guthaus 41fba9d27c Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
Matt Guthaus c6503dd771 Modify unit tests to reset options during init_openram so 
that they don't use old parameters after a failure.
 2018-07-10 16:39:32 -07:00
Matt Guthaus d4cd8aff15 Change permissions of tests 2018-05-14 16:36:58 -07:00
Matt Guthaus f34c4eb7dc Convert entire OpenRAM to use python3. Works with Python 3.6. 
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
 2018-05-14 16:15:45 -07:00
mguthaus c1c1ba38a3 Fix unit test to have fanout. 2018-02-16 11:53:38 -08:00
Matt Guthaus 2413304f4e Update replica bitline test for new parameters. Add small test and a larger test. 2018-02-07 15:15:19 -08:00
Matt Guthaus 56770f558f Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
Matt Guthaus 7a172873a3 Update unit tests to load verify after config file. Start magic DRC. 2018-01-12 10:24:49 -08:00
Matt Guthaus abee235963 Rewrite the parameterized transistor and gate classes. 
Changes propagate through all designs.
All modules use instance and layout pins.
 2017-12-12 15:04:01 -08:00