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OpenRAM
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919 Commits

Author SHA1 Message Date
mrg 8c911f70b9 Build changes. 
Don't pull docker since it will be build by CI.
Shuffle tests to stagger technologies and test types.
 2022-03-06 10:31:43 -08:00
mrg 4fac069c3c Skip hspice tests in docker 2022-03-01 14:44:04 -08:00
mrg c12c006799 Add verbose option 2022-03-01 10:50:49 -08:00
mrg 38494458e3 Fix incorrect port 1w to 1r 2022-03-01 10:44:56 -08:00
mrg c223c1ad1c Run docker pull before running all tests for regression 2022-03-01 10:33:40 -08:00
mrg 184888b370 Skip 16 way test for now 2022-02-28 12:03:01 -08:00
mrg 27b4d2edb1 Add 16 way mux SRAM tests 2022-02-28 11:53:24 -08:00
mrg 82c2bc329f Split bank and col mux tests. 2022-02-23 15:39:32 -08:00
mrg 6389d4ac82 Skip all func tests 2022-02-23 15:31:15 -08:00
mrg 1742927751 Split port data tests into individual tests 2022-02-23 11:12:32 -08:00
mrg a75d9fcc76 Fix failing test output of Makefile 2022-02-11 13:11:24 -08:00
mrg a35ab45843 Conditionally set TEST_TECHS. Skip pand4 for sky130. 2022-02-10 11:30:20 -08:00
mrg c471823626 Run individual tests on all technologies by default 2022-02-10 11:18:52 -08:00
mrg 51097b2c8b Revert rm in makefile 2022-02-02 09:38:27 -08:00
mrg 39f1199b63 Always delete result subdir to prevent bad and ok simultaneously 2022-02-02 09:36:19 -08:00
mrg 2d2620d21a Remove dir from bad tests 2022-02-02 07:11:13 -08:00
mrg c75968401c Update for detailed skips. Added some sky130 skips. 2022-02-08 16:04:43 -08:00
mrg 16238af584 Print failing tests before exit 2022-02-08 13:07:37 -08:00
mrg 4d62cbd345 Move pdk paths to docker invocation 2022-02-08 12:05:39 -08:00
mrg b1e1763e14 Fix PDK path for freepdk45 and list FAILED tests explicitly at end. 2022-02-08 11:35:29 -08:00
mrg b641bc8eef Check proper subdir for bad files 2022-02-07 16:30:18 -08:00
mrg a3d3aa514b Add target for all technologies 2022-02-07 11:27:10 -08:00
mrg ee97d87bdf Fix total regress pass or fail check. 2022-02-06 12:36:22 -08:00
mrg 89688de3cf Remove outside of docker space 2022-02-06 09:48:30 -08:00
mrg 93c6565b66 Add total failure of tests 2022-02-06 09:13:36 -08:00
mrg 8653b88206 Remove working temp directories 2022-02-06 09:06:20 -08:00
mrg d716a1c361 Don't stop on fail, archive all results, create .bad file on fail. 2022-02-05 07:50:06 -08:00
mrg e45e2f77c9 Rework regression to use docker. 2022-02-04 17:43:48 -08:00
mrg 049751ae1f FreePDK45 running with klayout and Sky130 running with magic. 2022-02-03 10:19:28 -08:00
mrg 63a6168b35 Merge branch 'dev' into klayout 2022-02-01 11:57:56 -08:00
mrg 06d391b3e3 Keep files during runs in Makefile 2022-01-13 14:41:24 -08:00
mrg 34dd46c918 Exceptions for sky130 spare columns tests 2021-12-17 10:30:43 -08:00
mrg 4fa084f272 Add 1rw decoder test 2021-12-17 10:18:20 -08:00
mrg edf3a701e4 Update options for arguments and readme. 2021-11-16 14:33:35 -08:00
mrg c102ed728c Move tests to test Makefile 2021-11-03 11:36:19 -07:00
mrg e6a009312e Move mem reg before usage for compatibility 2021-10-13 09:46:02 -07:00
mrg 178f1197ca Use spare rows only for sky130 2021-09-07 16:49:11 -07:00
mrg 83f2d14646 Fix unit test errors. 
Skip test 50s for now.
Change golden power values in xyce delay test.
 2021-09-07 14:07:22 -07:00
mrg b2389fe00f Change tolerance to 30% 2021-09-03 14:04:39 -07:00
mrg 90a4ad4d75 Update size of 30 config tests to 2 bits. 2021-07-28 12:05:31 -07:00
mrg 0464ec3f16 Skip 50 tests 2021-07-01 16:38:39 -07:00
mrg 55f09d00a4 Make replica_column sky130 friendly 2021-07-01 16:15:13 -07:00
mrg 879f945aa7 Add risc5 functional tests 2021-07-01 16:13:14 -07:00
mrg 6be24d4c6c Only 25 cycles 2021-07-01 12:50:20 -07:00
mrg 3d2b192682 Add conditional spare row/col to a couple unit tests 2021-07-01 12:49:30 -07:00
mrg 927de3a240 Debugging then disabling spare cols functional sim for now. 2021-06-29 15:47:53 -07:00
mrg c4aec6af8c Functional fixes. 
Off by one error of max address with redundant rows.
Select reads 3x more during functional sim.
 2021-06-29 09:33:44 -07:00
Hunter Nichols 294ccf602e Merged with dev, addressed conflict in port data 2021-06-21 17:23:32 -07:00
mrg 67877175b2 Fix error in no spare column verilog 2021-06-18 08:41:26 -07:00
Jesse Cirimelli-Low 7b7c72706a merge in dev 2021-06-17 09:49:32 -07:00