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OpenRAM
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36 Commits

Author SHA1 Message Date
mrg f6587badad Improve supply routing for ring and side pins 2021-05-28 10:58:30 -07:00
mrg 2b5013fd69 Config example changes 2021-05-26 16:14:48 -07:00
mrg a0e263b14a Add vdd/gnd pins to the side. 2021-05-03 15:14:15 -07:00
mrg 01f4ad7a11 Add sky130 config examples 2021-04-22 13:53:23 -07:00
mrg 671470f5f2 Skywater changes. 
Default 1 thread and no temp subdirectory.
Add skywater setup/hold golden data
Add CLI option for simulation threads (-m)
Add compatibility mode option and nomodcheck for ngspice to speed up sky130 model loading.
Make subdir when using default /tmp dir.
Pass num_threads so temp subdirs are created.
 2021-03-22 15:48:14 -07:00
mrg 049d3ffcaf Remove extra test file 2021-03-01 15:25:39 -08:00
mrg 9e7c04a43a Merge lekez2005 changes WITHOUT control logic change. 2021-03-01 15:19:30 -08:00
ota2 9d025604ff Simulate calibre extracted netlists without requiring extra layout ports 2021-02-27 19:29:18 -05:00
mrg 33bc9a597c Remove dashes for Python module name warning. 2021-02-15 08:19:08 -08:00
mrg 348001b1c8 Supply tree uses signal grid. PEP8 cleanup. 2020-12-21 13:51:50 -08:00
mrg 6cfa20731c Consistent naming in example configs 2020-11-18 09:59:38 -08:00
mrg 2f12c77668 Create single port memory config examples. 2020-11-03 14:42:56 -08:00
mrg d209e8d9a3 Disable perimeter pins for now 2020-11-03 13:35:34 -08:00
mrg bd9bac6635 Fixed nominal_corner_only parameter. 2020-10-30 15:52:07 -07:00
mrg f97ae723f0 Remove extraneous config files. 2020-10-23 13:56:27 -07:00
mrg 35c91168f7 Add load/slew scale option to config files 2020-10-16 13:52:36 -07:00
jcirimel 4a1a7e637e merge in dev 2020-10-07 11:54:07 -07:00
mrg ba432669a1 Add various riscv examples 2020-10-06 16:25:44 -07:00
jcirimel efdc171b14 make split wl specific to each port 2020-09-23 00:08:34 -07:00
jcirimel d22164bd48 single port progess 2020-09-14 18:11:38 -07:00
mrg b7c43ae674 Fix 1w/1r example 2020-07-23 14:17:13 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
mrg 2011974e01 Make drc and lvs errors a member variable. Run only once. 2020-07-13 12:49:24 -07:00
jcirimel 101eb28112 revert example scn4m to non netlist only 2020-02-09 23:52:11 -08:00
Jesse Cirimelli-Low b107934672 fix styling 2020-02-06 12:15:52 +00:00
Jesse Cirimelli-Low 30604fb093 add multiport support for pex labels 2020-01-28 00:28:55 +00:00
Matt Guthaus be4893839b Remove old drc/lvs override name 2019-12-16 10:05:52 -08:00
Matt Guthaus 0cdd3af1aa Change default nominal corners to false and enable in test config. 2019-11-29 12:08:53 -08:00
Matt Guthaus 84c7146792 Fix some pep8 errors/warnings in pgate and examples. 2019-10-06 17:30:16 +00:00
Matt Guthaus 07ecf52b9f Add giant example for front-end mode 2019-04-01 15:49:01 -07:00
Matt Guthaus 74f904a509 Cleanup options for front-end. Improve info output. 2019-04-01 10:35:17 -07:00
Matt Guthaus c3e074c069 Add option for routing supplies. Off by default, but enabled in unit test config files. 2019-04-01 09:58:59 -07:00
Matt Guthaus 1f1426b97c Add auto-detect of custom bitcells 2019-02-25 16:10:34 -08:00
Matt Guthaus 4577d380f9 Add example 1w/1r 2019-02-24 09:57:34 -08:00
Matt Guthaus 82a09be026 Move inspect into if statement for runtime 2019-01-30 08:42:25 -08:00
Matt Guthaus 5de7ff3773 Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench. 2019-01-11 14:15:16 -08:00