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OpenRAM
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175 Commits

Author SHA1 Message Date
Matt Guthaus 40410cc9f5 Clean up code to work when no drc/lvs/pex is found. 2017-11-14 15:31:58 -08:00
Matt Guthaus 257cd62d25 Remove tools from tech file and have search order preference like spice. 2017-11-14 15:27:03 -08:00
Matt Guthaus 3e0f39cd8e Skeleton code for indirect DRC/LVS/PEX tools. 2017-11-14 14:59:14 -08:00
Matt Guthaus 29c5ab48f0 Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
Matt Guthaus 8071dcc0f3 Add customsim (xa) as optional simulator. Fix regex to support scientific notation. Go through list of preferred simulators in order. Always abort if command-line simulator not found. 2017-11-12 10:42:41 -08:00
Jun Chen 054e4d3c28 my change 2017-11-11 16:54:04 +09:00
Matt Guthaus 95f1a24f72 Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
Matt Guthaus 0744cbcc60 Merge branch 'master' into dev 2017-11-09 09:11:26 -08:00
Matt Guthaus 05158f104b Removed unnecessary sram_tb.v file. 2017-10-17 15:51:31 -07:00
mguthaus 5c10aebc0f Fix bug in multifinger ptx. Replace LEF file with new snapped layout. 2017-10-06 16:23:23 -07:00
Matt Guthaus 10a8531813 Fix new offset snap problems in wordline drive. Fix ptx multifinger pin bug. Add new add_center_rect function. 2017-10-06 15:30:15 -07:00
Matt Guthaus a9797d12ab Added pins to the ptx class. Modified pin class to do lazy write of GDS shapes to allow removal of pins. 2017-10-05 17:35:05 -07:00
Matt Guthaus b2043bef11 Fix small delay difference in unit test 21_hspice_delay_test. 2017-10-05 08:13:53 -07:00
Matt Guthaus 69e44c78d8 Upgrade version to 1.01 2017-10-04 20:18:30 -07:00
Matt Guthaus 59a0394c2b Update LEF files with modified blockages. 2017-10-04 20:17:30 -07:00
Matt Guthaus 788f3d9122 4-bank SRAMs are now working. 2017-10-04 18:05:45 -07:00
Matt Guthaus 21c77645d3 Remove LVS correspondence points for multibank in single bank. 2017-09-29 16:44:24 -07:00
Matt Guthaus e06e1691c8 Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
Matt Guthaus d29dd03373 SRAM single bank passing DRC/LVS. 2017-09-13 15:46:41 -07:00
Matt Guthaus 3ea003c367 Fix 1-way single bank LVS bug. Full SRAM still not functional. 8-way has DRC error. 2017-09-11 14:30:52 -07:00
Matt Guthaus d17711c394 Fixed several LVS errors. Bank passes LVS for 2-way and 4-way, but not 1-way or 8-way. 2017-08-24 16:22:14 -07:00
Matt Guthaus cf940fb15d Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
Matt Guthaus 857b997367 Modify LEF output to have all capital LAYER. Remove extra space before new lines. 2017-08-15 08:21:54 -07:00
Matt Guthaus d77216d6dd Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays. 2017-08-07 10:24:45 -07:00
Matt Guthaus 7ec20a72c8 Fix old unit test golden result 2017-07-06 14:16:02 -07:00
Matt Guthaus 20d8c0bc45 Improved characterizer. 2017-07-06 08:42:25 -07:00
mguthaus e92cb9ecef Removed array_type from ms_flop_array since it is extraneous code. 2017-07-03 12:08:50 -07:00
Matt Guthaus 8a821e13ac Convert print to functional type call like Python 3. Perform error checking that requires Python >2.7 <3.0 for better error checking. 2017-06-12 15:02:48 -07:00
mguthaus 6e90bf0d6d Enable output filename and path to be in config file. Command line will over-ride config file. 2017-06-12 14:37:15 -07:00
mguthaus a840209c08 Fix unit tests to be DRC clean. 2017-06-07 10:29:53 -07:00
Matt Guthaus 93389ac723 Add test to reroute after route fails. Disable GDS route debug info unless verbosity is more than 0. 2017-06-07 10:10:18 -07:00
mguthaus 5960324ca6 Simplify sparse add for grid map. 2017-06-07 09:38:57 -07:00
mguthaus c061b985ba Fix missing map key check in blocked get/set. 2017-06-06 17:12:19 -07:00
Matt Guthaus 8b5e92e582 Merge branch 'master' of github.com:mguthaus/OpenRAM 2017-06-06 11:06:35 -07:00
Matt Guthaus 4e97e385e1 New lib file. Tolerances were off. 2017-06-06 11:06:16 -07:00
Matt Guthaus d67a7149ab Small fixes to last commit. Remove grid pin debug output. Remove extraneous function calls to add grids. 2017-06-05 15:46:50 -07:00
mguthaus 11bb105545 Mark inaccessible off-grid pins as blocked. Improve on-grid pin analysis, but not quite good enough yet. 2017-06-05 14:42:56 -07:00
mguthaus 16063cc9a0 Merge branch 'master' into router 2017-06-05 13:12:51 -07:00
Matt Guthaus 3e2b6e42d4 Merge branch 'router' 2017-06-05 09:08:17 -07:00
Matt Guthaus d20ea65923 Fix lib test to enable spice simulation. Fixed bug with change in default argument. 2017-06-05 09:07:52 -07:00
Matt Guthaus 0acbf43908 Fix lib test to enable spice simulation. Fixed bug with change in default argument. 2017-06-05 09:03:51 -07:00
mguthaus f32912f07c Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity. 2017-06-02 11:11:57 -07:00
Matt Guthaus b18f0e9905 Moved TODO items to GitHub issues. 2017-05-31 15:47:01 -07:00
Matt Guthaus 384e169b5b Modified unit tests: one for analytical model, one for characterization. 2017-05-31 14:59:22 -07:00
Matt Guthaus 367d4168ad Merge branch 'master' into router 2017-05-31 14:04:31 -07:00
Matt Guthaus d31b1862a3 Improved router debugging and return error if unable to route. 2017-05-31 13:59:49 -07:00
Matt Guthaus 8cc63560f8 Merge branch 'master' into router 2017-05-31 12:09:04 -07:00
Matt Guthaus 424c7b7e64 Made back-annotation and analytical modelling boolean options. Default is false. 2017-05-31 08:12:17 -07:00
Matt Guthaus 46c56863ee Bin Wu fixed unit test to pass with analytical delay option 2017-05-31 08:01:42 -07:00
Matt Guthaus 34e180b901 Analytical delay model from Bin Wu. Unit test not passing. 2017-05-30 12:50:07 -07:00