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OpenRAM
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3957 Commits

Author SHA1 Message Date
Mik Igor 3227f1bb52
Merge aa2cf88870 into ea15a81443 2025-08-01 02:09:32 +00:00
mrg bc1cc36ade Merge branch 'whitespace_fix' of github.com:TristanRobitaille/OpenRAM into dev 2024-11-12 09:49:00 -08:00
Tristan Robitaille 1f5fe62456 Added whitespace between : and 'minimum_period', '1kOhm' and 'min_pulse_width' as required by Liberty file standard 2024-11-10 14:31:52 +01:00
mole99 85e242fa27 Add gf180mcu ROM example 2024-02-03 11:31:58 +01:00
Eren Dogan 0cf60a6a18 Give u+x permissions for rom tests 2024-01-20 17:49:52 -08:00
Eren Dogan 55e5c425e9 Fix same file error and enable passing tests 2024-01-20 08:38:18 -08:00
Eren Dogan 14c219d9f1 Enable working tests from disabled stamps 2024-01-19 15:16:30 -08:00
Eren Dogan 855139bc4e Add Makefile target to run broken tests only 2024-01-19 15:15:52 -08:00
Eren Dogan 0a1de57cae Update copyright year 2024-01-03 14:32:44 -08:00
mole99 8032fa75a4 Add LEF output for ROM 2023-12-21 08:07:49 +01:00
Hadir Khan 9d6052b86c fix for matching the layout vs verilog port names for rom 2023-12-20 15:30:07 -08:00
Eren Dogan efd43c3191 Merge branch 'dev' into issue_fix 2023-12-06 13:30:22 -08:00
Eren Dogan 7531e38cad Remove unused local variable 2023-12-05 11:18:58 -08:00
Eren Dogan 39a66fcb87 Fix some lint errors 2023-12-05 11:16:22 -08:00
Eren Dogan 6cfb22959c Remove unused imports 2023-12-05 11:08:32 -08:00
SWalker 6bd437cfa8 Fixed bug that made metal-metal vias think they were well contacts 2023-11-07 14:27:11 -08:00
SWalker b9570b8ddf removed gf180 specific code from ptx 2023-11-07 01:01:05 -08:00
SWalker ce1861f342 proper output rom bank output layer 2023-10-31 23:24:21 -07:00
SWalker d161cc55a5 fixed missing broken stamp 2023-10-31 23:24:21 -07:00
SWalker a45e16bff5 re-added rom tests to regression ignore for freepdk45 2023-10-31 23:24:21 -07:00
SWalker 26068fd2e1 more ptx fixes 2023-10-31 23:24:21 -07:00
SWalker b453aa23c2 fix ptx minwidth calculation for freepdk45 2023-10-31 23:24:21 -07:00
SWalker 5378a308c1 updated gitignore and regression make to ignore gf180. Fixed issue with rom decoder routing 2023-10-31 23:24:21 -07:00
SWalker 1f35855c6d remove old rom test 2023-10-31 23:24:21 -07:00
SWalker 9b99e6c124 bunch of cleanups to core rom classes 2023-10-31 23:24:21 -07:00
SWalker ddba3b3718 move vdd pins around to make routing nice 2023-10-31 23:24:21 -07:00
SWalker 5c22e382b5 add parameter to make routing horizonal vdd rails easier 2023-10-31 23:24:21 -07:00
SWalker 4b3af38727 change min rail to contact spacing for long gf180 contact extend 2023-10-31 23:24:21 -07:00
SWalker 565e3f6814 flatten ptx in extraction and renumber test based on importance 2023-10-31 23:24:21 -07:00
SWalker 3271c5e73c fixing drc on rom bank, mostly spacing tweaks 2023-10-31 23:24:21 -07:00
SWalker 75f7a5847f fixing contact placement for gf180 in rom 2023-10-31 23:24:21 -07:00
Sage Walker b279791762 added control buf test 2023-10-31 23:24:21 -07:00
SWalker a544abebf7 fixed contact area issue 2023-10-31 23:24:21 -07:00
Sage Walker cb8567c66f spacing tweaks for gf180 address control gate 2023-10-31 23:24:21 -07:00
Sage Walker d6cb15c82d Switched to GF180D for extra metal layers, Fixed drc parameters so contacts are valid. ptx.py modified to achieve proper layer placement with gf180. ROM array and precharge DRC clean. 2023-10-31 23:24:21 -07:00
Sage Walker 0040efb86f workaround for magic drc in gf180 2023-10-31 23:24:21 -07:00
Sage Walker b0a0226e87 rom array compatability changes 2023-10-31 23:24:21 -07:00
Hadir Khan 7ce11eba52 added pwell as a non-routing layer 2023-10-31 23:24:21 -07:00
Hadir Khan 81b62ab13b added gf180mcu as the test tech target 2023-10-31 23:24:21 -07:00
Mik Igor aa2cf88870
Fix tabs/spaces in globals.py 
Some tabs/extra spaces were inserted accidentally by GitHub text editor in the tech_name param validation, so has to remove them.
 2023-10-27 01:35:04 +02:00
Mik Igor 173e47ae45
Validate tech_name in config file iterating over technology dir 
We're now validating the tech_name param specified by the user in the config file listing all the subfolders present in the technology folder. If the technology specified is not present as folder, we will emit an error and quit.
 2023-10-27 01:29:27 +02:00
Mik Igor 5811c5ce99
FIX: scn3me_subm typo 
Fixed incorrect tech_name "scn3m_subm" (correct is "scn3me_subm", note the 3mE).
 2023-10-27 00:49:31 +02:00
Mik Igor 189824429c
Add freepdk45 to debug error in tech_name validation 
Ooops, I forgot to add the freepdk45 mention in the debug.log string
 2023-10-27 00:45:32 +02:00
Mik Igor 123e43e942
Add freepdk45 to tech_name validation in compiler/globals.py 
Forgot to add the freepdk45 tech_name in validation
 2023-10-27 00:40:55 +02:00
Mik Igor ce2b11ebd9
Validate tech_name param in compiler/globals.py 
We need to pre-validate the tech_name param in the config file or python will comply with a non-very-descriptive message that can confuse the user about where's the problem.
 2023-10-26 23:53:03 +02:00
Eren Dogan fe379297be Add timestamps to the log file 2023-10-05 14:55:05 -07:00
Sam Crow a5412902c6 all control logic tests pass now 2023-09-27 16:38:57 -07:00
Sam Crow bf49ea744e force multi-delay chain pinouts to be user configurable 2023-09-27 13:15:45 -07:00
Sam Crow 5b282df667 Revert "add drc style drc(full) to run_drc.sh on Tim Edwards recommondation" 
This reverts commit c4a14b9354.
 2023-09-26 11:37:04 -07:00
Sam Crow c4a14b9354 add drc style drc(full) to run_drc.sh on Tim Edwards recommondation 2023-09-25 14:14:27 -07:00