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OpenRAM
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4,543 Commits 4 Branches 63 Tags 78 MiB
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3731 Commits

Author SHA1 Message Date
Eren Dogan 1c274afa46 Include blockages in the routing area after generating nodes 2023-07-22 21:30:40 -07:00
Eren Dogan 06b8f3b2be Prevent supply ring from overlapping existing pins 2023-07-22 19:25:26 -07:00
Eren Dogan 48b556c43a Fix even more DRC errors in graph router 2023-07-22 14:07:27 -07:00
Eren Dogan 8354de654f Fix precision of blockage node centers 2023-07-21 12:24:20 -07:00
Eren Dogan 3e3265c416 Add new snap_to_grid function for graph router 2023-07-21 09:55:36 -07:00
Eren Dogan 44b2e4589c Don't use multiple when inflating shapes 2023-07-21 08:30:46 -07:00
Eren Dogan 7ee1dcef54 Simplify inflated_from logic 2023-07-21 08:26:54 -07:00
Eren Dogan 5ce193c2dd Snap node vectors to grid to prevent precision errors 2023-07-19 18:32:22 -07:00
Eren Dogan e8c3cf0a94 Remove nodes inside routables that can cause DRC errors 2023-07-18 22:36:14 -07:00
Eren Dogan 53d00f5b34 Merge branch 'dev' into gridless_router 2023-07-18 10:00:00 -07:00
Eren Dogan 5ef964d01f Merge branch 'dev' into gridless_router 2023-07-18 09:31:20 -07:00
Eren Dogan b5983fbfd6 Prevent via DRC errors 2023-07-17 16:30:19 -07:00
Eren Dogan 6e051e7f06 Avoid DRC errors when routing the same type of pin 2023-07-17 15:43:48 -07:00
Eren Dogan 38110a55e1 Connect graph nodes better by hopping over removed nodes 2023-07-17 15:02:36 -07:00
Eren Dogan e501e0ef4f Cleanup graph for gridless router 2023-07-16 20:41:58 -07:00
Eren Dogan 983cf13ccf Fix spacing for gridless router 2023-07-16 20:25:15 -07:00
Eren Dogan 094e71764a Change option name for the gridless router 2023-07-13 12:16:58 -07:00
Eren Dogan 71e4a5ab6c Rename gridless router files 2023-07-13 12:07:55 -07:00
Eren Dogan 813a67fea9 Add more comments for gridless router 2023-07-13 11:29:51 -07:00
Sam Crow 89d8441108 Merge branch 'dev' into delay_ctrl 2023-07-10 14:31:26 -07:00
Samuel Crow 042a3ed14f
skip non-scmos delay control tests for now 2023-07-10 14:28:19 -07:00
Sam Crow 4e649aad6b fix typo bug in spice comments code 2023-07-10 13:21:24 -07:00
Eren Dogan 6b0b4c2def Create fake pins on the ring and route others to them 2023-07-10 09:24:16 -07:00
Eren Dogan 4a61874888 Add supply ring pins around the layout area 2023-07-09 18:53:21 -07:00
Sam Crow b91c628acf Merge branch 'dev' into delay_ctrl 2023-07-06 08:45:03 -07:00
Sam Crow 468c972acb add optional guard band to delay chain sizing 2023-07-05 16:34:42 -07:00
Sam Crow d65ccfcc95 fix column mux without rbl start_bit to 0 2023-07-05 13:17:46 -07:00
Sam Crow b4a9784835 model vth delay swing delay 2023-07-05 12:17:48 -07:00
Sam Crow 5235cf9667 model p_en and wl_en delays in delay chain sizing 2023-07-03 17:02:11 -07:00
Eren Dogan bb35ac2f90 Include new wires while routing the pins 2023-07-03 14:04:26 -07:00
Eren Dogan 0938e7ec9a Fix probes not being blocked correctly 2023-07-03 13:34:27 -07:00
Eren Dogan 78be525ea0 Use minimum spanning tree to route same type of pins together 2023-07-01 16:14:56 -07:00
Sam Crow e1865083d7 incomplete work on improved delay modeling 2023-06-29 14:44:42 -07:00
Eren Dogan 5bf629f3e5 Prevent DRC violations for vdd and gnd pins 2023-06-28 20:55:49 -07:00
Sam Crow 91694fdae3 add fixme note for unit conversion 2023-06-28 14:05:42 -07:00
Sam Crow 28ea93bd0a convert 1-indexing to 0-indexing 2023-06-25 11:03:10 -07:00
Sam Crow 006eacd6d0 add pinout message output 2023-06-25 10:46:58 -07:00
Sam Crow 8992c0fb68 first approximation of delay values 2023-06-20 16:22:03 -07:00
Eren Dogan a47bc7ebee Prevent multiple dog-legs in non-preferred direction 2023-06-15 11:08:13 -07:00
Sam Crow dbc9de6c9a implement relationship between delay pinouts 2023-06-14 17:10:07 -07:00
Gary Mejia 9a36cce7ae Fixed formatting on all files 2023-06-14 12:28:36 -07:00
Gary Mejia b9e61f346a Merge branch 'dev' into openROM-verilogoutput 
To test recent changes with ROM verilog output
 2023-06-14 12:26:07 -07:00
Gary Mejia a3284e8b47 Fixed module from writing syntax issues 2023-06-13 17:30:38 -07:00
Sam Crow bf516a927d add skeleton for delay chain sizing 2023-06-13 13:44:32 -07:00
Sam Crow fee90283b9 add spacing and a comment 2023-06-12 16:56:44 -07:00
Gary Mejia 692acd2066 Verilog ROM model created for testing 2023-06-12 15:35:54 -07:00
Sam Crow 96a1d400fa add single port bank test for norbl 2023-06-12 12:50:50 -07:00
Sam Crow 266bcd9cf2 consolidate failing xyce delay tests to one in skip list 2023-06-11 14:52:26 -07:00
Sam Crow 854bff9dce add norbl bank tests to sky130 skipped tests 2023-06-08 13:22:12 -07:00
Sam Crow 7048a072e2 add local/global array sky130 skipped tests 2023-06-08 13:16:27 -07:00