21 Commits

Author	SHA1	Message	Date
Matt Guthaus	09a429aef7	Update unit tests to all use the sram_factory	2019-03-06 14:12:24 -08:00
Matt Guthaus	6dd959b638	Fix error in 8mux test. Fix comment in all tests.	2018-11-02 16:34:26 -07:00
Matt Guthaus	563ff77d44	Add sram_config class. Rename port variables for better description.	2018-08-31 12:03:28 -07:00
Michael Timothy Grimes	e118cc2d5c	Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport	2018-08-29 16:06:50 -07:00
Michael Timothy Grimes	aeaab13d28	Unit tests for pbitcell now passing, so commenting out skip line. Also gave pbitcell_array useful names in unit test for easier debugging	2018-08-29 16:05:13 -07:00
Matt Guthaus	41fba9d27c	Add sketch for power grid routing code	2018-08-29 15:34:16 -07:00
Matt Guthaus	8752d799b4	Skip pbitcell tests for now	2018-08-28 10:45:50 -07:00
Matt Guthaus	9ffba4b052	Add +x permissions on precharge and pbitcell tests	2018-08-13 09:57:10 -07:00
Michael Timothy Grimes	ecd4612167	altered bitcell, pbitcell, and bitcell array modules to accomodate additional bitline reference functions	2018-08-05 19:43:59 -07:00
Michael Timothy Grimes	27ab411146	fixed error I missed in pbitcell_array test	2018-07-26 09:02:52 -07:00
Michael Timothy Grimes	2388ddbfb0	deleting code added in error to pbitcell_array_test during previous commit	2018-07-12 23:55:54 -07:00
Michael Timothy Grimes	ba43b986ae	merging changes with pbitcell_array test	2018-07-12 23:51:44 -07:00
Michael Timothy Grimes	a64ca423c6	changing pbitcell_array test to include an important permutation of the design	2018-07-12 23:45:47 -07:00
Matt Guthaus	c6503dd771	Modify unit tests to reset options during init_openram so ... that they don't use old parameters after a failure.	2018-07-10 16:39:32 -07:00
Matt Guthaus	32099646cf	Add back fix to revert bitcell from pbitcell.	2018-06-29 12:45:26 -07:00
Matt Guthaus	ac7aa4537c	Remove uniqe pbitcell id since it isn't needed. Convert dos EOL to unix EOL characters. Convert python2.7 to python3 in pbitcell.	2018-06-29 11:49:02 -07:00
Matt Guthaus	fa17d5e7f3	Change permissions of tests to be executable so you don't have to type python each time.	2018-06-29 11:36:30 -07:00
Michael Timothy Grimes	e19a422696	simplfying calculations in pbitcell and changing pbitcell_array_test to check different port combinations	2018-05-31 17:39:51 -07:00
Michael Timothy Grimes	3971835f24	changed pbitcell_array tests in regards to addition of read/write ports in pbitcell	2018-05-10 09:40:43 -07:00
Michael Timothy Grimes	65735c08e2	fixed bitcell_array to work with different sized pbitcells, changed sizing in pbitcell to minimize space between inverters	2018-03-08 16:39:26 -08:00
Michael Timothy Grimes	820a8440c9	adding unit test for bitcell array using pbitcell	2018-03-06 16:36:11 -08:00