13 Commits

Author	SHA1	Message	Date
Michael Timothy Grimes	0cc077598e	Added member functions to bitcell.py and pbitcell.py for use in bitcell_array.py. bitcell_array now used only one function for every type of bitcell.	2018-03-15 12:02:38 -07:00
Michael Timothy Grimes	65735c08e2	fixed bitcell_array to work with different sized pbitcells, changed sizing in pbitcell to minimize space between inverters	2018-03-08 16:39:26 -08:00
Michael Timothy Grimes	0ea5d0b6a7	making changes to bitcell_array to account for the addition nets from the multiported bitcells	2018-03-06 17:03:21 -08:00
mguthaus	28fe49d069	Change RBL to allow stages and FO for configuration	2018-02-16 11:51:01 -08:00
mguthaus	1297cb4e40	Convert dff to VTG transistors in 45nm. Correct pin order in dff library cell.	2018-02-16 10:40:05 -08:00
Matt Guthaus	2e3e95efda	Change ratio of delay line and RBL size. Need to tune it better automatically.	2018-02-14 16:50:08 -08:00
Matt Guthaus	9559421ca8	Connect dff array clk in rows and columns.	2018-02-14 16:46:26 -08:00
Matt Guthaus	2d87dcda46	dff array done except for clock net	2018-02-14 16:03:29 -08:00
Matt Guthaus	0804a1eceb	Add new DFF. Create DFF module. Start dff_array, not tested.	2018-02-14 15:16:28 -08:00
mguthaus	767990ca3b	Update golden lib tests. Add new generic SCMOS models. Fix tech error with new msflop_in_cap name.	2018-02-13 15:54:50 -08:00
Matt Guthaus	f457091bba	Fix typo in precharge.	2018-02-12 15:34:01 -08:00
Matt Guthaus	e32b0b8f7a	Change precharge input from clk to en	2018-02-12 15:32:47 -08:00
Matt Guthaus	7100d6f904	Organize top-level files into subdirs.	2018-02-09 10:25:24 -08:00