Matt Guthaus
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19d46f5954
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Finalized separation of netlist/layout creation.
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2018-08-27 14:18:32 -07:00 |
Michael Timothy Grimes
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b8ae21a52b
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made multi-port changes to sram. This commit will allow all levels of openram to pass unit tests
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2018-08-20 22:11:24 -07:00 |
Michael Timothy Grimes
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19ca0d6c2a
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Changing control logic names to match naming scheme for multi-port. din[0] to din0[0], s_en to s_en0, addr[0] to addr0[0], etc. Sram level should pass unit tests for single port but will not currently pass for multi-port
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2018-08-18 16:51:21 -07:00 |
Matt Guthaus
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8900edbe12
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Finalize single bank clock routing.
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2018-08-14 10:36:35 -07:00 |
Matt Guthaus
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3420b1002c
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Connect data and column DFF clocks in 1 bank.
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2018-08-14 10:09:41 -07:00 |
Matt Guthaus
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b7525a14c2
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Change DIN to DOUT in characterizer. Spacing dff flops down by m2 not m1 pitch.
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2018-07-25 15:50:49 -07:00 |
Matt Guthaus
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7c254d540d
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Change channel route api to use pin maps instead of an insteads for cases where there are multiple instances that have the pins (e.g. decoders)
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2018-07-25 11:37:06 -07:00 |
Matt Guthaus
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f7a2766c29
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First draft of naive channel route in hierarchy_layout. It doesn't implement horizontal conflicts or try to minimize the number of channels.
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2018-07-25 11:13:30 -07:00 |
Matt Guthaus
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3f57853969
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Use lower case names except for leaf cells and top level
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2018-07-18 15:10:57 -07:00 |
Matt Guthaus
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a9c0ec5549
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Add LVS correspondence points to each bank type
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2018-07-18 14:29:04 -07:00 |
Matt Guthaus
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ffc866ef78
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Single bank working except for channel routing error in 4-way case.
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2018-07-17 14:40:04 -07:00 |
Matt Guthaus
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7a69fc1bca
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Add col addr routing and data routing
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2018-07-17 14:24:44 -07:00 |
Matt Guthaus
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ac22b1145f
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Convert bank to use create_bus routines.
Modify control logic to have correct offset in SRAM.
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2018-07-16 14:13:41 -07:00 |
Matt Guthaus
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f3ae29fe0b
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Getting single bank to work reliably. Removed tri_gate from bank
for now. Will add it in multibank arrays only. Not needed for
separate DIN and DOUT ports.
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2018-07-13 14:45:46 -07:00 |
Matt Guthaus
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0c23efe49b
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Reference local sram instance in sram.py.
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2018-07-13 09:30:14 -07:00 |
Matt Guthaus
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e6b1fcb44c
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Refactor banks to use inheritance with a top-level SRAM wrapper class.
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2018-07-12 10:30:45 -07:00 |
Matt Guthaus
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d95a1925d4
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Refactor banked SRAM into multiple files and dynamically load in SRAM
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2018-07-10 14:17:09 -07:00 |