luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,853 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

66 Commits

Author SHA1 Message Date
Bugra Onal abd18ab832 Moved freepdk sense amp dout pin away from gnd pin 2023-05-23 15:08:06 -07:00
Bugra Onal 027b93ab83 Added buff to sense_amp in freepdk45 2023-04-12 11:49:55 -07:00
mrg 7195d81736 Adjust WL and GND for contacted via2 spacing. 2022-04-19 10:32:37 -07:00
mrg 68d0a56423 Fix WL to gnd spacing for grounded wordlines. 2022-04-04 16:02:47 -07:00
mrg 111533f0b0 Move power pins to horizontal or vertical layer in all cells. 2022-03-31 16:36:19 -07:00
mrg 83e5848728 Change FreePDK and SCMOS 2rw cell to share gnd power rail. 2022-03-30 13:48:53 -07:00
mrg 67b51ff7f5 Move vdd pin in freepdk45 sense amp from dout 2022-03-06 12:20:54 -08:00
mrg 9b90a44d4a Move output in freepdk45 sense amp down to prevent router conflict with supply 2022-02-25 16:20:47 -08:00
mrg 8081bea708 Shrink 70nm contacts to 65nm 2021-09-16 15:28:39 -07:00
ota2 8403749fec Add Q and Qbar labels 2021-02-27 18:27:08 -05:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg cf63499e76 Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
mrg 80070dff41 Move write_driver din left to avoid control signal in spare columns. 2020-07-16 14:47:14 -07:00
mrg 20324ab3c4 Revert write driver pin spacing 2020-06-28 14:55:58 -07:00
mrg e774314add Separate write driver pins by M3 pitch 2020-06-28 14:14:48 -07:00
mrg a7ee17eb2d Move output of sense amp to side like other techs 2020-06-26 15:29:27 -07:00
mrg 157926960b Flip freepdk45 flop, dff_buf route layer change 2020-06-09 13:48:16 -07:00
jsowash d5e331d4f3 Connected en together in write_mask_and_array. 2019-08-09 14:27:53 -07:00
mrg ae9dbe203d Add freepdk45 dummy cells 2019-07-03 14:53:44 -07:00
Matt Guthaus 6cdc870091 Copy 1rw/1r cell to 1w/1r. 2019-02-24 09:54:45 -08:00
Hunter Nichols 1e87a0efd2 Re-added new width 1rw,1r bitcells with flattened gds. 2018-12-05 20:43:10 -08:00
Hunter Nichols 009f6e94ea Reverted gds/sp to reprevious widths. 2018-12-05 17:42:31 -08:00
Hunter Nichols 05773ad16e Altered 1rw,1r cell and replica to match tx widths pbitcell in freepdk45 2018-11-14 11:53:13 -08:00
Matt Guthaus 83aadc47c9 Remove layer 230 labels from library cells 2018-11-09 11:12:31 -08:00
Matt Guthaus 05c25eb506 Remove layer 230 labels from library cells 2018-11-09 11:08:20 -08:00
Matt Guthaus 9fe64b486c Remove layer 230 labels from library cells 2018-11-09 11:02:19 -08:00
Matt Guthaus c01f0f5274 Merge branch 'dev' into fix_rbl_cell_connections 2018-11-05 16:38:46 -08:00
Matt Guthaus de6d9d4699 Change freepdk45 rbl cell too. 2018-11-05 11:02:11 -08:00
Hunter Nichols b00fc040a3 Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos. 2018-11-01 12:29:49 -07:00
Hunter Nichols 9321f0461b Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r. 2018-10-31 00:06:34 -07:00
Hunter Nichols 6efe0f56c2 Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array. 2018-10-26 00:08:13 -07:00
Hunter Nichols 8e243258e4 Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell. 2018-10-26 00:08:12 -07:00
Hunter Nichols 4f08062268 Added custom 1rw+1r bitcell. Testing are currently failing. 2018-10-22 17:02:21 -07:00
Matt Guthaus f8fc7c12b3 Remove ms_flop and replace with dff. Might break setup_hold tests. 2018-09-13 11:02:28 -07:00
Matt Guthaus d721fae5b0 Change labels in replica cell for freepdk45 too 2018-09-04 14:33:14 -07:00
Michael Timothy Grimes d8cb3653e0 changing case of pins in handmade cell_6t for freepdk45 2018-05-22 14:19:26 -07:00
Matt Guthaus 85b7b73903 Flip sense amp y axis 2018-04-23 10:19:26 -07:00
Matt Guthaus 269d553857 Move sense amp to tri gate routing to M3... not ideal. 2018-04-23 09:14:18 -07:00
Matt Guthaus e1f4c933e1 Flip sense amp and increase pin size 2018-04-20 17:04:26 -07:00
Matt Guthaus c75eafe085 Fix some errors 2018-04-18 09:37:33 -07:00
Matt Guthaus e2f93a0a99 Fix via overlap DRC error 2018-04-11 15:48:40 -07:00
Matt Guthaus ef99d13f1b Fix via overlap DRC error 2018-04-11 15:46:44 -07:00
Matt Guthaus 6640d3491d Tri gate and array supply to M2 and M3 2018-04-11 15:11:47 -07:00
Matt Guthaus 06c132b695 Fix drc overlap error 2018-04-11 15:00:56 -07:00
Matt Guthaus 21bc5b7d05 Fix drc overlap error 2018-04-11 14:59:04 -07:00
Matt Guthaus 14ff20fc9e Fix drc overlap error 2018-04-11 14:56:59 -07:00
Matt Guthaus d1862eda90 Fix drc overlap error 2018-04-11 14:55:04 -07:00
Matt Guthaus 46c18f53ba Add M2 vias in ms_flop 2018-04-11 14:10:57 -07:00
Matt Guthaus 0e6720be66 Fix write driver gnd pin layer text 2018-04-11 09:34:13 -07:00
Matt Guthaus 4f8ab78ee2 Change write driver supply pins to M2 2018-04-11 09:29:54 -07:00