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luke/OpenRAM
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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-02 11:08:01 +02:00
Code Issues Packages Projects Releases Wiki Activity
4,807 Commits 5 Branches 63 Tags
07fa78e00c82cd76b271c27fcf1d98bbb45674bd
Commit Graph
8 Commits
Author SHA1 Message Date
SWalker 4bb586c949 decoder nand custom cell 2023-10-31 23:24:21 -07:00
Sage Walker d6cb15c82d Switched to GF180D for extra metal layers, Fixed drc parameters so contacts are valid. ptx.py modified to achieve proper layer placement with gf180. ROM array and precharge DRC clean. 2023-10-31 23:24:21 -07:00
Hadir Khan 698020301c updates to add the port order overwrite attribute, ignore drc/lvs attribute and pwell as a non-routing layer 2023-10-31 23:24:21 -07:00
hadirkhan10 b9fd172e44 corrected the pin mapping 2023-10-31 23:24:21 -07:00
hadirkhan10 de7a248ff0 added the cell property definitions 2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low a904874978 passing gf180 parameterized gate tests 2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low d18a4f8c7c additional tech commits 2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low a18d62c430 rename gf180 to gf180mcu 2023-10-31 23:24:21 -07:00
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