luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,958 Commits 5 Branches 63 Tags 79 MiB
Commit Graph

658 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low a5c879f510 Merge remote-tracking branch 'openram_local/array_gen' into merge/full-array-gen-into-dev 
# Conflicts:
#	technology/sky130/custom/sky130_col_cap_array.py
 2026-04-30 12:43:19 -07:00
Maarten Boersma 7382ea7dda
fix #279: expliticly extract single number from numpy array to meet stricter numpy>=2.4.0 code hygiene 2026-01-16 15:05:28 +01:00
Jesse Cirimelli-Low f3c1c5fbb2 Merge branch 'singleport_refactor' into array_gen 2025-02-24 23:26:28 -08:00
Eren Dogan 0a1de57cae Update copyright year 2024-01-03 14:32:44 -08:00
Hadir Khan 9d6052b86c fix for matching the layout vs verilog port names for rom 2023-12-20 15:30:07 -08:00
SWalker 6bd437cfa8 Fixed bug that made metal-metal vias think they were well contacts 2023-11-07 14:27:11 -08:00
SWalker 5c22e382b5 add parameter to make routing horizonal vdd rails easier 2023-10-31 23:24:21 -07:00
SWalker a544abebf7 fixed contact area issue 2023-10-31 23:24:21 -07:00
Sage Walker d6cb15c82d Switched to GF180D for extra metal layers, Fixed drc parameters so contacts are valid. ptx.py modified to achieve proper layer placement with gf180. ROM array and precharge DRC clean. 2023-10-31 23:24:21 -07:00
Hadir Khan 7ce11eba52 added pwell as a non-routing layer 2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low 0cba6a6050 single port sky130 crba passing lvs 2023-08-30 20:59:02 -07:00
Jesse Cirimelli-Low 8f2e4c6914 power ring working 2023-08-28 22:15:05 -07:00
Sam Crow bb47452baf reapply commit c8a06a1 patch that was incorrectly reverted 2023-08-15 11:07:04 -07:00
Sam Crow cd1b0f973d Revert pin/net spice object work 
This reverts commits 01116 6e3e9 2ced8 c67fd 2b9e7 bfabe 09aa3 5907c aa717 478c7 45b88 d0339 e15fe 7581d c8c43 146ef
 2023-08-14 18:44:51 -07:00
Jesse Cirimelli-Low 0111620c91 deepcopy overide for instance 2023-08-11 13:45:24 -07:00
Jesse Cirimelli-Low e23289d5ae merge in dev 2023-08-10 17:04:45 -07:00
Jesse Cirimelli-Low 6f4ee4ad2d pass modules by pointer not value 2023-08-09 14:06:35 -07:00
Jesse Cirimelli-Low 8d8f243f99 scmos passing with odd sizses again 2023-07-27 18:39:18 -07:00
Jesse Cirimelli-Low 8a4b34dee1 proper tiling 2023-07-26 18:05:36 -07:00
Jesse Cirimelli-Low cb21443e2d start of pattern refactor 2023-07-24 23:25:35 -07:00
Sam Crow 6e3e964c12 cleanup net_spice docstrings 2023-07-19 12:45:41 -07:00
Sam Crow f41537b508 Merge branch 'char' into STA-refactor 2023-07-19 12:35:22 -07:00
Sam Crow 2ced895b32 add BIAS pin type back to valid types 2023-07-19 12:15:47 -07:00
Sam Crow c67fdd8bd8 fix insts typo 2023-07-19 12:15:21 -07:00
Bugra Onal d53353b5be Merge branch 'dev' into char 2023-07-19 12:06:34 -07:00
Sam Crow 2b9e70d318 remove line ending whitespace from comment 2023-07-19 10:51:19 -07:00
Sam Crow bfabe64f33 fix pin/net dictionary deepcopy-ing 2023-07-18 16:14:38 -07:00
Sam Crow 5907cbb3e2 remove pins overwrite from contact class 2023-07-18 16:12:42 -07:00
Sam Crow aa71785bd5 fix circular import with pin and net 2023-07-18 11:28:30 -07:00
Sam Crow 478c76c1ca get connections from spice objects in instances 2023-07-18 10:50:50 -07:00
Sam Crow 8a441bc68b Merge branch 'dev' into STA-refactor 2023-07-17 16:35:31 -07:00
Sam Crow 45b88889e4 use pin and net objects in connect_inst 2023-07-17 16:04:56 -07:00
Sam Crow d0339a90e6 change spice_nets and spice_pins to dicts 2023-07-17 15:36:57 -07:00
Sam Crow e15feb2361 change nets list to dictionary 2023-07-17 15:36:22 -07:00
Sam Crow 7581df2255 change pins to OrderedDict 2023-07-17 15:22:35 -07:00
Sam Crow c8c43f75d9 add spice nets and a way to connect them to pins 2023-07-14 16:18:10 -07:00
Sam Crow 146efc5070 implement pin_spice object 2023-07-13 16:45:05 -07:00
Sam Crow 89d8441108 Merge branch 'dev' into delay_ctrl 2023-07-10 14:31:26 -07:00
Sam Crow 4e649aad6b fix typo bug in spice comments code 2023-07-10 13:21:24 -07:00
Sam Crow b91c628acf Merge branch 'dev' into delay_ctrl 2023-07-06 08:45:03 -07:00
Sam Crow 91694fdae3 add fixme note for unit conversion 2023-06-28 14:05:42 -07:00
Gary Mejia 9a36cce7ae Fixed formatting on all files 2023-06-14 12:28:36 -07:00
Gary Mejia a3284e8b47 Fixed module from writing syntax issues 2023-06-13 17:30:38 -07:00
Gary Mejia 692acd2066 Verilog ROM model created for testing 2023-06-12 15:35:54 -07:00
Bugra Onal dae275c508 Merge branch 'dev' into char 2023-04-12 12:00:31 -07:00
Jacob Walker fef9902c45 rom base passing tests with top level routing 2023-03-30 11:30:50 -07:00
Jacob Walker af0209ec96 passing code style 2023-03-30 11:30:50 -07:00
Jacob Walker bbf2cd2913 Changes for test generation and simulation 2023-03-30 11:30:50 -07:00
Jacob Walker f7aed247fd column control and address precharge 2023-03-30 11:30:50 -07:00
Bugra Onal 613146520e Merge branch 'library' into char 2023-02-23 15:11:39 -08:00