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array_gen-to-dev
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Author SHA1 Message Date
Sam Crow b91c628acf Merge branch 'dev' into delay_ctrl 2023-07-06 08:45:03 -07:00
Sam Crow 468c972acb add optional guard band to delay chain sizing 2023-07-05 16:34:42 -07:00
Bugra Onal 071670bef0 Removed import global 2023-07-05 14:29:51 -07:00
Sam Crow d65ccfcc95 fix column mux without rbl start_bit to 0 2023-07-05 13:17:46 -07:00
Sam Crow b4a9784835 model vth delay swing delay 2023-07-05 12:17:48 -07:00
Sam Crow 5235cf9667 model p_en and wl_en delays in delay chain sizing 2023-07-03 17:02:11 -07:00
Eren Dogan bb35ac2f90 Include new wires while routing the pins 2023-07-03 14:04:26 -07:00
Eren Dogan 0938e7ec9a Fix probes not being blocked correctly 2023-07-03 13:34:27 -07:00
Eren Dogan 78be525ea0 Use minimum spanning tree to route same type of pins together 2023-07-01 16:14:56 -07:00
Sam Crow e1865083d7 incomplete work on improved delay modeling 2023-06-29 14:44:42 -07:00
Eren Dogan 5bf629f3e5 Prevent DRC violations for vdd and gnd pins 2023-06-28 20:55:49 -07:00
Sam Crow 91694fdae3 add fixme note for unit conversion 2023-06-28 14:05:42 -07:00
vlsida-bot 3620d56790 Bump version: 1.2.17 -> 1.2.18 v1.2.18 2023-06-27 00:22:04 +00:00
Jesse Cirimelli-Low 14f8008c4f Update index.md 
fix typo in index.md
 2023-06-26 15:37:42 -07:00
Sam Crow 28ea93bd0a convert 1-indexing to 0-indexing 2023-06-25 11:03:10 -07:00
Sam Crow 006eacd6d0 add pinout message output 2023-06-25 10:46:58 -07:00
vlsida-bot 3cd3a63419 Bump version: 1.2.16 -> 1.2.17 v1.2.17 2023-06-24 16:55:37 +00:00
Eren Dogan 3ada5347eb Set shell in the Makefile 2023-06-23 20:59:28 -07:00
Eren Dogan 92c8770472 Fix publications 2023-06-23 20:38:49 -07:00
Sam Crow 8992c0fb68 first approximation of delay values 2023-06-20 16:22:03 -07:00
Eren Dogan a47bc7ebee Prevent multiple dog-legs in non-preferred direction 2023-06-15 11:08:13 -07:00
Sam Crow dbc9de6c9a implement relationship between delay pinouts 2023-06-14 17:10:07 -07:00
vlsida-bot 542df33878 Bump version: 1.2.15 -> 1.2.16 v1.2.16 2023-06-14 23:14:13 +00:00
Gary Mejia 9a36cce7ae Fixed formatting on all files 2023-06-14 12:28:36 -07:00
Gary Mejia b9e61f346a Merge branch 'dev' into openROM-verilogoutput 
To test recent changes with ROM verilog output
 2023-06-14 12:26:07 -07:00
Gary Mejia a3284e8b47 Fixed module from writing syntax issues 2023-06-13 17:30:38 -07:00
Sam Crow bf516a927d add skeleton for delay chain sizing 2023-06-13 13:44:32 -07:00
Sam Crow fee90283b9 add spacing and a comment 2023-06-12 16:56:44 -07:00
Gary Mejia 692acd2066 Verilog ROM model created for testing 2023-06-12 15:35:54 -07:00
Sam Crow 96a1d400fa add single port bank test for norbl 2023-06-12 12:50:50 -07:00
Sam Crow 266bcd9cf2 consolidate failing xyce delay tests to one in skip list 2023-06-11 14:52:26 -07:00
Sam Crow 854bff9dce add norbl bank tests to sky130 skipped tests 2023-06-08 13:22:12 -07:00
Sam Crow 7048a072e2 add local/global array sky130 skipped tests 2023-06-08 13:16:27 -07:00
Sam Crow 44ed72b50d add has_rbl=True arg to tests 2023-06-08 13:10:03 -07:00
Sam Crow ce622952ef route rbl conditionally 2023-06-08 12:36:31 -07:00
Sam Crow a51b71d460 update copyright 2023-06-08 12:36:12 -07:00
Sam Crow 539dfc979a conform default behavior for sky130 custom modules to unit test 2023-06-07 17:31:12 -07:00
Sam Crow 973b5512f0 add new failing sky130 tests to skip list 2023-06-07 17:29:58 -07:00
Sam Crow dcf95460d0 sort sky130 skipped tests numerically 2023-06-07 16:09:18 -07:00
Sam Crow 9256ae8c00 fix typos and standardize multiport control logic tests 2023-06-07 16:04:54 -07:00
samuelkcrow afd3b782b9 remove cs_bar signal bus from all control logics 2023-06-07 15:53:15 -07:00
samuelkcrow a48842ff72 fix code format issues from 00 test 2023-06-07 15:52:25 -07:00
samuelkcrow b9492051b6 use control_logic_base in control_logic_delay 2023-06-07 15:51:19 -07:00
Sam Crow a70dcc5c85 reword comments in replica bitcell array module 2023-06-06 14:43:18 -07:00
Sam Crow 9fdf8a8341 ommit rbl pins in sram_1bank when appropriate 2023-06-06 13:15:17 -07:00
Sam Crow 157935c915 update test/module imports related to delay control 2023-06-06 13:12:20 -07:00
Eren Dogan 15b4e4dbe8 Fix DRC spacing in Hanan router 2023-06-05 19:33:45 -07:00
Sam Crow 5fef78dbfa Merge branch 'no_rbl' into delay_ctrl 2023-06-05 16:31:07 -07:00
Sam Crow 2f5d3b6faf Merge branch 'dev' into delay_ctrl 2023-06-05 16:24:48 -07:00
Sam Crow df827fbd3d add norbl whole sram test 2023-06-05 15:26:26 -07:00