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4879 Commits

Author SHA1 Message Date
Akash Levy 3d4bf57745 Merge from upstream 2025-07-02 11:25:18 -07:00
Miodrag Milanović 54013c6da7
Merge pull request #5162 from YosysHQ/micko/attrmap 
Make attrmap able to alter memory attributes as well
 2025-06-30 15:24:04 +02:00
Akash Levy 435f773cc4 Add back submod -noclean 2025-06-27 14:26:11 -07:00
Akash Levy 414c9e8898 Fix annotate_cell_fanout issue by double uniquifying... hopefully should fix the issue? 2025-06-25 22:09:43 -07:00
Akash Levy 981a89aa1e Add hierarchy separator option to submod pass 2025-06-23 03:38:00 -07:00
Akash Levy 7e9e4c7afe
Merge branch 'YosysHQ:main' into main 2025-06-23 02:30:24 -07:00
Akash Levy 828cfc0039 Fix issue with buffer naming uniquification 2025-06-23 02:25:34 -07:00
George Rennie 170933ecb0
Merge pull request #5165 from georgerennie/george/opt_dff_uaf 
opt_dff: don't remove cells until all have been visited to prevent UAF
 2025-06-20 23:33:26 +01:00
Krystine Sherwin beaca05b40
Include boxes in attrmap 
Rename `selected_members` iterator to memb.
Add comment on `selected_processes` loop for clarity.
 2025-06-21 09:49:56 +12:00
Akash Levy 283faf3bf9 Merge from upstream 2025-06-13 10:19:49 -07:00
Emil J c0f52c6ead
Merge pull request #5167 from YosysHQ/emil/fix-splitnets-single-bit-vector 
splitnets: handle single-bit vectors consistently
 2025-06-11 22:47:48 +02:00
Akash Levy 819fde9329 Add debugon pass 2025-06-10 16:41:17 -07:00
Akash Levy 447a73ea86
Merge branch 'YosysHQ:main' into main 2025-06-09 14:51:56 -07:00
N. Engelhardt 0b19f628e9
Merge pull request #5172 from YosysHQ/nak/reduce_warning_spam 2025-06-08 06:50:56 +00:00
George Rennie 8c38e2081d opt_dff: don't emit cells until all have been visited to prevent UAF 2025-06-06 23:46:07 +01:00
N. Engelhardt f1dea78603 don't warn for every blackbox from verific 2025-06-06 15:37:42 +02:00
Neil Deo 093bf7ed7e Fix getPort issue to pass yosys tests 2025-06-05 14:38:38 -07:00
Emil J. Tywoniak 239c265093 splitnets: handle single-bit vectors consistently 2025-06-05 10:58:06 +02:00
George Rennie 19cdbc5a0c opt_dff: don't remove cells until all have been visited to prevent UAF 2025-06-04 21:02:21 +01:00
Miodrag Milanovic 784de0f6e3 Make attrmap able to alter memory attributes as well 2025-06-04 08:01:21 +02:00
Krystine Sherwin 785cabcb0f
abc9_ops: Skip opt_expr in proc 2025-05-31 12:16:37 +12:00
Krystine Sherwin ab0e3cc05f
Proc: Use selections consistently 
All `proc_*` passes now use the same module and process for loops, using `design->all_selected_modules()` and `mod->selected_processes()` respectively.
This simplifies the code, and makes the couple `proc_*` passes that were ignoring boxed modules stop doing that (which seems to have been erroneous rather than intentional).
 2025-05-31 12:04:42 +12:00
Akash Levy 3fc74be3e2
Merge branch 'YosysHQ:main' into main 2025-05-28 01:54:49 +02:00
Lofty e4ab6acb46 Add genlib support to abc_new 2025-05-27 09:47:29 +01:00
Akash Levy 3a23e772dd
Merge branch 'YosysHQ:main' into main 2025-05-24 12:11:52 -07:00
Emil J 18abf2d4f7
Merge pull request #5138 from YosysHQ/emil/libcache-verbose 
libcache: add -quiet and -verbose
 2025-05-24 00:05:46 +02:00
George Rennie e05b21cfae
Merge pull request #5140 from garytwong/typo-fix 
Fix typo ("exist" -> "exit").
 2025-05-23 13:01:57 +01:00
Gary Wong 4f0cbf2ee6 Fix typo ("exist" -> "exit"). 2025-05-22 18:52:33 -06:00
Akash Levy d520cb42cc
Merge branch 'YosysHQ:main' into main 2025-05-22 10:30:58 -07:00
George Rennie 6331f92d00
Merge pull request #5101 from georgerennie/george/opt_expr_shift_ovfl 
opt_expr: fix shift optimization with overflowing shift amount
 2025-05-22 15:16:19 +01:00
Akash Levy 3c7c004c31 Fix stuff 2025-05-15 15:27:12 -07:00
Akash Levy 3f94486a1c
Merge pull request #82 from donn/splitlarge 
splitlarge: new pass to split wide arithmetic operators
 2025-05-15 15:00:45 -07:00
Akash Levy 1f00bf0057 Bump yosys to latest 2025-05-15 14:44:26 -07:00
KrystalDelusion 4c72b0ecd8
Merge pull request #5116 from YosysHQ/krys/update_fst 
Update fstlib
 2025-05-16 09:22:52 +12:00
KrystalDelusion 3a5ce2df64
Merge pull request #5112 from YosysHQ/krys/on_shutdown 
design.cc: Use on_shutdown method
 2025-05-16 09:22:39 +12:00
KrystalDelusion f7888c607b
Merge pull request #5089 from YosysHQ/krys/cutpoint_whole 
cutpoint: Re-add whole module optimization
 2025-05-16 09:22:28 +12:00
Mohamed Gaber 1d9fbb6143 misc: review feedback, remove MUL vestiges 2025-05-15 18:01:13 +03:00
Mohamed Gaber 46ba89059a splitlarge: new pass to split wide arithmetic operators 
Adds a new pass, `splitlarge`, that recursively divides $add/$sub
cells into smaller cells until each cell's width doesn't exceed a
given max_width (128 by default.) An $add/$sub cell's width for
this purpose is defined as the higher of the widths of its two
inputs.

A test was written in Tcl for it, which tests this matrix:
- cell: $add/$sub
- b: unsigned, signed
- a: unsigned, signed

This is the first test for a Silimate pass in Tcl and thus
`run-test.sh` was modified to include it.
 2025-05-15 17:45:08 +03:00
Emil J 3823157c25
Merge pull request #5080 from akashlevy/muldiv_c 
Add `muldiv_c` peepopt
 2025-05-15 11:03:25 +02:00
George Rennie 748600c167
small whitespace cleanup (#5119) 2025-05-14 15:18:57 +02:00
Akash Levy 1990c1fac5 Reduce pass verbosity 2025-05-13 20:42:47 -07:00
Akash Levy d308ecdbcf Fix warnings with block curly braces 2025-05-13 20:42:28 -07:00
Akash Levy 769aaa113c Get boolopt src attribution working for dress 2025-05-13 20:05:16 -07:00
Akash Levy d6975c1d5f Fix src attr inheritance in opt_share 2025-05-13 20:05:16 -07:00
Akash Levy 2e030bfdfd Refactor bmuxmap attribute inheritance 2025-05-13 20:05:16 -07:00
Akash Levy f97587db61 Fix fanout buffer src annotation and refactor naming 2025-05-13 20:05:16 -07:00
Akash Levy 13e053fb11 Fixups 2025-05-12 14:49:37 -07:00
Akash Levy 8171f04cbf Add preliminary boolopt src attribution support 2025-05-12 02:30:36 -07:00
Krystine Sherwin d0b9a0cb98
sim.cc: Move cycle check 
Calling `throw dst_end_of_data_exception()` when the desired number of cycles has been reached means that the fst reader can't tidy up after itself and leads to memory leaks.
This doesn't happen when the `-stop` flag is used because the `Yosys::FstData` struct tracks the end time and skips the outer callback if the simulation has gone past the desired end time.
Move cycle checking into the inner callback along with the time checking means that the outer callback no longer needs to throw an exception in order to stop checking further values, while still allowing the fst reader to finish reading and deallocate memory.
 2025-05-12 12:48:01 +12:00
Krystine Sherwin cc402ee065
libs/fst: Update upstream 
libfst is no longer included in gtkwave and instead has its own repo.  There has also been some refactoring, so the patches need to update to match, as does sim.cc.
 2025-05-12 10:21:06 +12:00