luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix annotate_cell_fanout issue by double uniquifying... hopefully should fix the issue?

This commit is contained in:
Akash Levy 2025-06-25 22:09:43 -07:00
parent 981a89aa1e
commit 414c9e8898
1 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
passes/silimate/annotate_cell_fanout.cc
View File

@ -346,11 +346,13 @@ void fixfanout(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::
for (SigChunk chunk : sigToBuffer.chunks()) {
std::vector<std::pair<RTLIL::SigSpec, Cell *>> buffer_chunk_outputs;
for (int i = 0; i < num_buffers; ++i) {
std::string wireName = generateSigSpecName(module, sigToBuffer, "_wbuf", index_buffer).c_str();
std::string cellName = generateSigSpecName(module, sigToBuffer, "_fbuf", index_buffer).c_str();
RTLIL::IdString wireName = generateSigSpecName(module, sigToBuffer, "_wbuf", index_buffer);
RTLIL::IdString cellName = generateSigSpecName(module, sigToBuffer, "_fbuf", index_buffer);
RTLIL::Cell *buffer = module->addCell(cellName, ID($buf));
bufferActualFanout[buffer] = 0;
RTLIL::SigSpec buffer_output = module->addWire(wireName, chunk.size());
if (module->count_id(wireName) != 0)
log_warning("Wire name %s already exists somehow...\n", wireName.c_str());
RTLIL::SigSpec buffer_output = module->addWire(module->uniquify(wireName), chunk.size());
insertedBuffers.emplace(buffer, buffer_output.as_wire());
buffer->setPort(ID(A), chunk);
buffer->setPort(ID(Y), sigmap(buffer_output));