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Fix getPort issue to pass yosys tests

This commit is contained in:
Neil Deo 2025-06-05 14:38:38 -07:00
parent 6530a3d150
commit 093bf7ed7e
1 changed files with 3 additions and 1 deletions
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4
passes/techmap/abc.cc
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@ -1208,7 +1208,9 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
dict<std::string, int> cell_stats;
for (auto c : mapped_mod->cells())
{
c->attributes = sig_to_driver_attrs[mapped_sigmap(module->wire(remap_name(c->getPort(ID::Y).as_wire()->name)))];
// SILIMATE: set output port to either Y or Q depending on the cell's ports
RTLIL::IdString output_port_name = (c->hasPort(ID::Y)) ? ID::Y : ID::Q;
c->attributes = sig_to_driver_attrs[mapped_sigmap(module->wire(remap_name(c->getPort(output_port_name).as_wire()->name)))];
if (builtin_lib)
{
cell_stats[RTLIL::unescape_id(c->type)]++;