mirror of https://github.com/YosysHQ/yosys.git
Fix warnings with block curly braces
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769aaa113c
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d308ecdbcf
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@ -716,11 +716,12 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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for (auto cell : module->cells())
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for (auto &conn : cell->connections())
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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for (auto bit : sigmap(conn.second)) {
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if (GetSize(cell->attributes) > 0)
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sig_to_driver_attrs[bit] = cell->attributes;
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else
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sig_to_driver_attrs[bit] = bit.wire->attributes;
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}
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signal_map.clear();
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signal_list.clear();
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@ -1189,7 +1190,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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for (auto w : mapped_mod->wires()) {
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RTLIL::Wire *orig_wire = nullptr;
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RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire));
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if (orig_wire != nullptr)
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if (orig_wire != nullptr) {
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if (sig_to_driver_attrs.count(sigmap(orig_wire))) {
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wire->attributes = sig_to_driver_attrs[sigmap(orig_wire)];
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sig_to_driver_attrs[mapped_sigmap(wire)] = wire->attributes;
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@ -1199,6 +1200,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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} else {
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log_debug("No driver attributes found for wire %s\n", orig_wire->name.c_str());
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}
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}
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if (markgroups) wire->attributes[ID::abcgroup] = map_autoidx;
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design->select(module, wire);
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}
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