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17956 Commits

Author SHA1 Message Date
Akash Levy f74ac17a5f Undo the terrible upstream changes that break everything... 2026-02-04 22:26:06 -08:00
Akash Levy 09fd53aaae Update abc 2026-02-04 17:01:27 -08:00
Akash Levy d3ab45c2fa
Merge branch 'YosysHQ:main' into main 2026-02-04 15:53:43 -08:00
Akash Levy dbeeb7a7cf
Merge pull request #98 from Silimate/nr_cleanup 
Nr cleanup
 2026-02-04 15:49:01 -08:00
AdvaySingh1 8d22f6d7e1 Merged with main 2026-02-04 13:00:22 -08:00
AdvaySingh1 607ef02339 Added abc_max_node_retention_origins flag in AbcConfig struct 2026-02-04 12:12:04 -08:00
AdvaySingh1 16b5a8e350 ABC: added -M flag for nMaxOrigins 2026-02-04 12:02:31 -08:00
AdvaySingh1 43027720d2 Fixed no sources log error to only output error if node_retention mode is on 2026-02-04 10:22:24 -08:00
Emil J 8bbde80e02
Merge pull request #5631 from rocallahan/cleanup-compare-signals 
Clean up `compare_signals()` in `opt_clean`
 2026-02-04 17:45:05 +01:00
Emil J 2aa0e1d009
Merge pull request #5629 from rocallahan/remove-zero-wires 
Avoid scanning entire module in `Module::remove()` if there are no wires to remove
 2026-02-04 17:44:24 +01:00
Emil J 992e64342c
Merge pull request #5621 from rocallahan/remove-opt-sort 
Remove `Design::sort()` calls from optimization passes
 2026-02-04 16:55:56 +01:00
Akash Levy 48e7b5a167 Let's go back to a simpler time for abc... 2026-02-04 04:33:19 -08:00
Akash Levy c57c49873e Please just stop modifying yosys... 2026-02-04 03:48:58 -08:00
Akash Levy ea6b968618
Merge pull request #102 from Silimate/merge2 
Merge2
 2026-02-04 02:54:00 -08:00
Akash Levy 241852eebd Test merge from upstream 2026-02-04 02:07:01 -08:00
Akash Levy af7e124c26
Merge pull request #101 from Silimate/yosys_abc_test1 
Small abc update to see what happens
 2026-02-04 01:45:56 -08:00
Akash Levy dd08ba75bc
Merge pull request #100 from Silimate/negopt-pass-pr 
Add negopt pass with comprehensive pattern matching
 2026-02-04 01:44:45 -08:00
Akash Levy 3bffeee622
Merge pull request #99 from Silimate/sim 
Activity annotation will use timescale from VCD
 2026-02-04 01:26:25 -08:00
Akash Levy 715e062bcd Merge branch 'main' into negopt-pass-pr 2026-02-04 00:15:53 -08:00
Akash Levy 0e0740a3a0
Remove unnecessary blank line in abc.cc 2026-02-04 00:08:42 -08:00
Akash Levy 33bcfe26dd Merge branch 'main' into sim 2026-02-03 23:57:24 -08:00
Miodrag Milanović 776b4d06a6
Merge pull request #5669 from YosysHQ/release/v0.62 
Release version 0.62
 2026-02-04 08:55:31 +01:00
Akash Levy 23ed2ef523 Small abc update to see what happens 2026-02-03 23:55:25 -08:00
Miodrag Milanovic ddfa34d743 Next dev cycle 2026-02-04 08:54:38 +01:00
Akash Levy 807df40422 Undo the weird abc changes 2026-02-03 23:21:48 -08:00
Robert O'Callahan 7326bb7d66
Only reuse ABC processes if we're using yosys-abc and it was built with ENABLE_READLINE 
(cherry picked from commit 5054fd17d7b70f2df97360bb0f0cc1c92a6ffe72)
 2026-02-04 17:19:10 +13:00
tondapusili 643427d9c9 Add negopt pass with comprehensive pattern matching 
This commit introduces the negopt pass with pre/post optimization modes
for handling negation patterns in arithmetic circuits.

Pre-optimization patterns (expose for tree balancing):
- manual2sub: (a + ~b) + 1 → a - b
- sub2neg: a - b → a + (-b)
- negexpand: -(a + b) → (-a) + (-b) [with output width fix]
- negneg: -(-a) → a
- negmux: -(s ? a : b) → s ? (-a) : (-b)

Post-optimization patterns (cleanup/rebuild):
- negrebuild: (-a) + (-b) → -(a + b)
- muxneg: s ? (-a) : (-b) → -(s ? a : b)
- neg2sub: a + (-b) → a - b

All patterns use nusers() for fanout checking (standard Yosys style).
Comprehensive test coverage with positive/negative cases and formal
verification via equiv_opt.
 2026-02-03 17:21:21 -08:00
Stan Lee bea2a7d473 add few debug 2026-02-03 14:40:33 -08:00
Stan Lee ce959ec1bb fixes 2026-02-03 12:42:33 -08:00
Stan Lee 6620d098d4 lower verbosity 2026-02-03 12:05:14 -08:00
AdvaySingh1 0b96050933 Added tabbing in blifparse to match sorroundings 2026-02-03 08:44:16 -08:00
Advay Singh 941be57cae
Added design->select after setting strpool_attribute for non-special case cells 
Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
 2026-02-03 08:41:53 -08:00
Advay Singh e73c15750c
Update passes/techmap/abc.cc for WARNING: Source wire not 
Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
 2026-02-03 08:38:07 -08:00
AdvaySingh1 d097e536f2 Fixed log to log_error 2026-02-03 08:33:57 -08:00
Akash Levy 8e5d24aa6b Bump yosys to latest 2026-02-03 06:08:36 -08:00
Miodrag Milanovic fc11754557 Release version 0.62 2026-02-03 12:09:24 +01:00
Miodrag Milanović 6dbe03f0f5
Merge pull request #5667 from Logikable/vhdl 
Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT.
 2026-02-03 07:59:52 +01:00
github-actions[bot] 153ddc0c84 Bump version 2026-02-03 00:33:37 +00:00
AdvaySingh1 2f3ed06b9b ABC: Added setify to reduce number of entries 2026-02-02 15:30:49 -08:00
Sean Luchen 224549fb88 Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT. 
Signed-off-by: Sean Luchen <seanluchen@google.com>
 2026-02-02 15:26:03 -08:00
AdvaySingh1 1317cbbb62 ABC: Added r flag into Extra_UtilGetopt for IoCommandReadBlif 2026-02-02 14:13:18 -08:00
AdvaySingh1 07e21e763a ABC: Refactored fEnabled flag 2026-02-02 14:03:07 -08:00
AdvaySingh1 f452702017 Added abc.node_retention flag 2026-02-02 12:08:18 -08:00
KrystalDelusion 414b1b6019
Merge pull request #5651 from rocallahan/abc-error-nonfatal 
Handle ABC nonfatal "Error:" messages
 2026-02-03 08:55:05 +13:00
AdvaySingh1 47469c2490 Added re-added gateinit logic previously deleted 2026-02-02 10:32:32 -08:00
Emil J 59653da599
Merge pull request #5609 from nataliakokoromyti/upstream-design-run-pass 
Add Design::run_pass()
 2026-02-02 19:30:18 +01:00
AdvaySingh1 900f8408af Fixed read_until_abc_done 2026-02-02 10:27:33 -08:00
AdvaySingh1 b005f69e27 Added comments in blifparse.cc 2026-02-02 10:15:59 -08:00
AdvaySingh1 9646319098 Fixed source wire to be reset to nullptr so value isn't carried on 2026-02-02 10:10:01 -08:00
AdvaySingh1 15625f56ed Removed cmath arbitrary include 2026-02-02 10:08:41 -08:00