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Added design->select after setting strpool_attribute for non-special case cells 

Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
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Advay Singh 2026-02-03 08:41:53 -08:00 committed by GitHub
parent e73c15750c
commit 941be57cae
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1 changed files with 1 additions and 1 deletions
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passes/techmap/abc.cc
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@ -1753,7 +1753,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict<SigSpec, std::string> &
cell->setPort(conn.first, newsig);
}
cell->add_strpool_attribute(ID::src, src_pool); // SILIMATE: set src attribute from wire pool
design->select(module, cell);
}
for (auto conn : mapped_mod->connections()) {